TSMC this week held its Arizona fab 'first tool-in' ceremony, where alongside celebrating its first US fab, the company also announced major expansion plans for the production facility. The world's largest foundry is set to invest tens of billions of dollars in the next phase of its Fab 21 near Phoenix, Arizona, to significantly expand its capacity and start production of chips on its N3 process technologies there by 2026. (by which point N3 will be a trailing-edge node)

Construction of TSMC's Fab 21 phase 1 in Arizona was completed earlier this year, and this week the company began installation of production tools into the facility. The fab will be equipped with tools from companies like ASML, Applied Materials, KLA, Lam Research, and Tokyo Electroni in the next few quarters, and it is scheduled to come online in early 2024. The fab will be producing chips using various process technologies that belong to TSMC's N5 family, which now includes N5, N5P, N4, N4P, and N4X nodes. Production capacity of this phase of the fab will be around 30,000 wafer starts per month (WSPM), though the precise number will depend on actual technologies and designs.

Companies like AMD, Apple, and NVIDIA are set to run orders through Fab 21 phase 1 to produce their advanced chips in the U.S. for the first time in years. 

But that isn't all that TSMC has in store for Fab 21. The company has announced that they now intend to build a second fab on the site, further expanding their US production capacity and setting up an even newer production line.

The new Arizona fab will expand TSMC's capacity at the site to around 50,000 WSPM and will bring TSMC's total investments in the site to $40 billion. Notably, that's a $28B jump over the initial $12B investment TSMC made in their first Arizona fab, underscoring how costs continue to rise for newer fabs, but also that TSMC is becoming more comfortable with making larger infrastructure investments within the US. TSMC expects annual revenue from Arizona fabs to be in $10 billion per year ballpark, according to a Reuters report. Meanwhile, TSMC's clients using the fabs will generate about $40 billion in revenue selling products made by the foundry in the U.S.

Set to come online in 2026, the second Arizona fab will be starting life a generation ahead of its initial counterpart, producing chips on TSMC's N3 family of production nodes, which includes N3, N3E, N3P, N3S, and N3X. TSMC is expected to deliver its first N3 chips to a client in early 2023, so while the fab still represents cutting-edge technology as of the time of its inception, by the time it comes online it will technically be a trailing-edge fab. TSMC has previously indicated that they would be keeping leading-edge production within Taiwan – in large part because that's where their actual R&D takes place – so the company's updated Arizona fab plans are consistent with that stance.

With regards to capacity, the new Arizona fab, like its existing sibling, will be another "MegaFab" in TSMC parlance. That is to say a mid-range fab producing around 25,000 wafer starts per month. TSMC hasn't disclosed a specific output figure for just the new fab, but with Fab 21 slated to offer 20,000 WSPM, it looks like this fab will be a bit bigger, at closer to 30,000 WSPM. Still, with a combined capacity of 50,000 wafers per month, TSMC's Arizona facility is still among one of TSMC's smaller operations – 50,000 wafers is only half the production capacity a single one of TSMC's class-leading GigaFabs. So even with a second fab line, TSMC's US operations will only represent a relatively small fraction of the company's overall chip fab capacity.

Looking forward, TSMC has already begun construction of the second Arizona fab, and given the usual fab construction timelines, we can expect the shell to be complete by early 2024. After which it will take TSMC around another two years to equip it.

Gallery: TSMC Supplier Tool Photos

Meanwhile, TSMC is set to start producing chips using its N2 node in Taiwan in the second half of 2025. That node will use will be TSMC's first node to use their nanosheet-based gate-all-around field-effect transistors (GAAFETs), and over time will gain backside power delivery. Still, since not all products need a leading-edge node, TSMC won't have any trouble lining up customers for their N3 US domestic capacity.

"A strong, geographically diverse, and resilient supply chain is essential to the global semiconductor industry," said Lisa Su, chief executive and chairman of AMD. "TSMC's investment and expansion in Arizona is extremely important and mission critical for both the semiconductor industry and our extended ecosystem of partners and customers. AMD expects to be a significant user of the TSMC Arizona fabs and we look forward to building our highest performance chips in the United States."

Source: TSMC

As many of you noticed, AnandTech has spent several hours offline today. We are still in recovery mode at the moment (as I write this, the site has been restored to a copy from November 25^th), but now that our major restoration efforts are completed, I wanted to offer you guys a brief update on the status of AnandTech.

At around 13:00 UTC (5am PT) today, the on-site cloud storage for AnandTech’s hosting provider became corrupted. As a result, AnandTech (and some other sites) were brought offline. Due to the nature of the corruption and the need to begin restoration efforts ASAP, we opted to restore the site from an off-site cold storage backup, rather than trusting the questionable on-site storage.

This is the first time we’ve ever had to execute our off-site data recovery plan before. And while it meant AT took a bit longer to restore than would be ideal, ultimately everything worked out and proved the necessity for off-site backups.

We’re still working to restore content from the last few days. Articles will be back, but we’ve likely lost any comments and user account registrations/updates made since midday Friday. Sorry about that! And thank you for bearing with us during today's outage.

ASUS is introducing two versions of the GeForce RTX 4090 and 4080 in its Republic of Gamers and TUF Gaming lines, giving gamers stylish and robust options for the latest graphics cards.

Western Digital had announced new products in the WD_BLACK lineup back in May 2022 to augment their offerings in the gaming market. The WD_BLACK P40 Game Drive SSD was part of the set, and became widely available last quarter. Western Digital has positioned the portable drive (PSSD) as a mid-range alternative to the premium WD_BLACK P50 Game Drive SSD. Sporting a USB 3.2 Gen 2x2 (20 Gbps) interface, the drive launched at a much lower price point compared to the P50 despite the addition of RGB lighting to the case. What corners has Western Digital cut in this mid-range offering, and what do gamers have to lose in going with the P40 over competing PSSDs? This review provides some answers.

Intel is officially taking the wraps off the first member of their Raptor Lake-based NUC13 family today. The NUC13 Extreme (like the three previous Extreme NUCs) caters to the gamers and content creators requiring leading edge performance and high-end discrete GPU support. Unlike the mainstream NUCs which have been consistently maintaining an ultra-compact form-factor profile, the Extreme family has slowly grown in size to accommodate flagship CPUs and discrete GPUs. These systems integrate a motherboard in a PCIe add-in card form factor (the Compute Element) and a baseboard that provides additional functionality with PCIe slots and other I/O features. As a refresher, Intel created the NUC Extreme category with the introduction of the Ghost Canyon NUC family in 2019. This was followed by the Tiger Lake-based Beast Canyon NUC in 2021 and the Alder Lake-based Dragon Canyon NUC earlier this year. The latest member of this family is today's introduction - the Raptor Canyon NUC based on the Shrike Bay Compute Element.

The NUC Extreme family has grown in physical footprint with each generation, and the NUC13 Extreme is Intel's biggest one yet. Coming in at 317mm x 129mm x 337mm (13.7L), this is more of a traditional tower desktop than the NUCs that the market has grown accustomed to. However, this size has allowed Intel to integrate flagship components. The Shrike Bay Compute Element supports socketed LGA 1700 processors with a PL1 of 150W and PL2 of 250W (tau of 28s). The vertical centering of the baseboard within the case enables plenty of isolation between the Compute Element on the top and the discrete GPU on the bottom. Triple-slot dGPUs up to 12.5" in length are supported.

The NUC13 Extreme Kit comes in three flavors, while the Shrike Bay Compute Element itself has six variations. These allow system integrators and OEMs to offer a wide variety of systems targeting different market segments. The table below summarizes the key differences between the three NUC13 Extreme kits.

Each kit SKU corresponds to a NUC13SBB Shrike Bay Compute Element. In addition, Intel is also readying the NUC13SBBi(9/7/5)F variants that come with the KF processors - those Compute Elements do not have any Thunderbolt 4 ports. The HDMI port / graphics outputs are also not present. The three KF SKUs also forsake the 10GbE port.

The block diagram below gives some insights into the design of the system in relation to the I/O capabilities. Note that the system continues to use the Z690 chipset that was seen in the Dragon Canyon NUC.

PCIe x16 bifurcation (x8 + x8) is possible for the Gen 5 lanes. However, the baseboard design in the Raptor Canyon NUC kits does not support it. This is yet another aspect that OEMs could use to differentiate their Shrike Bay-based systems from the NUC13 Extreme.

Intel has provided us with a pre-production engineering sample of the flagship Raptor Canyon NUC (augmented with an ASUS TUF Gaming RTX 3080Ti GPU) for review, and it is currently being put through the paces. The 150W PL1 and microarchitectural advances in Raptor Lake have ensured that the benchmark scores are off the charts compared to the previous NUC Extreme models, albeit at the cost of significantly higher power consumption. On the industrial design side, I have been very impressed. By eschewing a fancy chassis and opting for a simple cuboid, Intel has ensured that all the I/O ports are easily accessible, installation of components is fairly straightforward, and cable management is hugely simplified. The increased dimensions of the chassis are well worth these advantages over the previous NUC Extreme models. Stay tuned for a comprehensive review later this week.

With AMD’s first-wave of Zen 4 CPUs now in the books with the Ryzen 7000 series, the consumer arm of AMD is now shifting its attention over to its graphics business. In a presentation that ended moments ago dubbed “together we advance_gaming”, Dr. Lisa Su and other AMD leaders laid out the future of AMD’s graphics products. And that future is the RDNA 3 architecture, which will be the basis of the new Radeon RX 7900 XTX and Radeon RX 7900 XT video cards.

The two cards, set to be released on December 13^th, will be the first products released using the RDNA 3 architecture. According to AMD, the new flagship 7900 XTX will deliver up to 70% more performance at 4K than their previous flagship, the 6950 XT. This performance boost comes curtesy of several architectural improvements in RDNA that cumulatively offer 54% higher performance per watt than RDNA 2, as well as higher clockspeeds courtesy of TSMC’s 5nm (and 6nm) processes, and higher overall power consumption.

The full-fledged RX 7900 XTX will be hitting the streets at $999. Meanwhile the second-tier RX 7900 XT will run for $899.

Following hot on the heels of AMD’s major CPU launch of the year – the Zen 4 architecture and Ryzen 7000 family – today AMD will be giving their GPU architecture its moment in the sun with their gaming-centric “together we advance_gaming” event. Today’s event will be all about AMD’s next-generation Radeon GPU architecture, RDNA 3, which among other things, promises a 50% improvement in performance-per-watt over the previous-generation RDNA 2 (Radeon RX 6000 series) parts.

Notably, unlike AMD’s CPU event back in August, AMD has held their (video) cards closer to their proverbial chest for this event. We know that it’s all about the RDNA 3 architecture, but AMD is being quieter about product information and details. For example, any “Radeon RX 7000 series” branding is completely absent from all of AMD’s official communiques. So while the Radeon RX 7000 series is still the branding we’re expecting to see, AMD is leaving themselves a noticeable amount of room to throw some curveballs here.

In any case, AMD has offered a few high-level details on the RDNA 3 architecture throughout the year. The biggest items disclosed thus far are that AMD is targeting another 50% increase in performance-per-watt, and that these new GPUs (Navi 3x) will be made on a 5nm process (undoubtedly TSMC’s). Past that, AMD hasn’t given any guidance on what to expect for performance.

One interesting aspect, however, is that AMD has confirmed that they will be employing chiplets with this generation of products. To what extent, and whether that’s on all parts or just some, remains to be seen. But chiplets are in some respects the holy grail of GPU construction, because they give GPU designers options for scaling up GPUs past today’s die size (reticle) and yield limits. That said, it’s also a holy grail because the immense amount of data that must be passed between different parts of a GPU (on the order of terabytes per second) is very hard to do – and very necessary to do if you want a multi-chip GPU to be able to present itself as a single device.

We’re also apparently in store for some more significant upgrades to AMD’s overall GPU architecture. Though what exactly a “rearchitected compute unit” and “optimized graphics pipeline” fully entail remains to be seen.

The answers to all that, and more, are coming up here in a few hours. So be sure to join us today, November 3^rd, at 1pm Pacific (20:00 UTC) for our full live blog coverage of AMD’s latest GPU announcements. We can’t wait!

In today's review, we are taking a look at the ValuePro VP1600ELCD, a popular low-cost UPS from CyberPower, the renowned US-based power systems manufacturer. As the name suggests, it is a product developed with value in mind, in an effort to entice home users and small business owners. Truly, features such as built-in AVR and completely silent operation are very enticing at this price range from a renowned brand name. As with all things that are too good to be true though, there are tradeoffs.

While always an interesting topic by default, corporate earnings reports in the tech industry have become especially important in the last few months, as the industry prepares to weather what’s expected to be the biggest downturn in demand in the last several years. Intel’s brutal Q2’22 report, which found the company losing money on a GAAP basis for the first time in 5 years, seems to have been a herald of things to come for the largest industry, with AMD and other companies since issuing earnings warnings ahead of their own Q3 reports. So as the first major tech company to publish their complete Q3’22 earnings report, Intel is once again likely to be a barometer of the tech industry’s performance over the past three months.

For the third quarter of 2022, Intel reported $15.3B in revenue, a $3.9B decline versus the year-ago quarter. Compared to Intel’s hash Q2 report, the company has returned to profitability, booking a cool billion dollars in net income, though this is still well below their historical norms. In fact, the company is still operating at a (GAAP) loss, booking an operating income of -$175M. For Q3 at least, it would appear that it’s Intel’s tax situation that’s pushing them into the black, with the company recording a $1.2B tax benefit.

Currently the majority of high-end processors are monolithic, but design methodologies are slowly but surely shifting to multi-chiplet modules as leading-edge fabrication technologies get more expensive to use. In the coming years multi-chiplet system-in-packages (SiPs) are expected to become much more widespread, and advanced 2.5D and 3D chip packaging technologies will gain importance. To accelerate and simplify development of 3D designs, TSMC this week established its 3DFabric Alliance.

While multi-chiplet SiPs promise to simplify development and verification of highly complex designs, they require brand-new development methodologies as 3D packages bring a number of new challenges. This includes new design flows required for 3D integration, new methods of power delivery, new packaging technologies, and new testing techniques. To make the best use of the benefits of TSMC's 2.5D and 3D packaging technologies (InFO, CoWoS, and SoIC), the chip development industry needs the whole ecosystem to work in concert on chiplet packaging – and this is what 3DFabric Alliance is designed to do.

“3D silicon stacking and advanced packaging technologies open the door to a new era of chip-level and system-level innovation, and also require extensive ecosystem collaboration to help designers navigate the best path through the myriad options and approaches available to them,” said Dr. L.C. Lu, TSMC fellow and vice president of design and technology platform.

TSMC's 3DFabric Alliance brings together developers of electronic design automation (EDA) tools, intellectual property providers, contract chip designers, memory manufacturers, advanced substrate producers, semiconductor assembly and test companies, and the groups making the equipment used for testing and verification. The alliance currently has 19 members, but over time it is expected to expand as new members join the group.

As the leader of the Alliance, TSMC will set certain ground rules and standards. Meanwhile members of 3DFabric Alliance will co-define and co-develop some of the specifications for TSMC's 3DFabric technologies, will gain early access to TSMC's 3DFabric roadmap and specs to align their plans with the foundry's plans as well as those of other members of the alliance, and will be able to design and optimize solutions that are compatible with the new packaging methods. 

Ultimately, TSMC wants to ensure that members of 3DFabric Alliance will offer its clients compatible and interoperable solutions that will enable quick development and verification of multi-chiplet SiPs that use 2.5D and 3D packaging. 

For example, to unify the design ecosystem with qualified EDA tools and flows, TSMC has developed its 3Dblox standard. 3Dblox covers various aspects of building multi-chiplet devices featuring 2.5D and 3D packaging methodologies (such as chiplet and interface definitions), including physical implementation, power consumption, heat dissipation, electro-migration IR drop (EMIR), and timing/physical verification.

“Through the collective leadership of TSMC and our ecosystem partners, our 3DFabric Alliance offers customers an easy and flexible way to unlocking the power of 3D IC in their designs, and we can’t wait to see the innovations they can create with our 3DFabric technologies,” added Lu.

Ultimately, TSMC envisions that the alliance will greatly simplify and streamline the process for developing more advanced chips, especially for small and mid-size companies that rely more heavily on outside IP/designs. For example, if a company wants to develop a SiP consisting of logic chiplets stacked together and connected to an HBM3-based memory subsystem, EDA software from Ansys Cadence, Synopsys, and Siemens will allow it to design compatible chiplets, IP providers will sell those blocks the designer does not already have, TSMC will produce silicon, memory producers will offer compatible HBM3 KGSDs (known good stack dies), and then Ase Technology will assemble everything together. Meanwhile companies that do not have their own engineers will be able to order the design of the whole SiP (or individual chiplets) through Alchip or GUC, and then update their product over time if needed without needing to redesign everything, as the SiP will be built in accordance with 3DFabric and 3Dblox standards. 

3Dblox is currently supported by four major EDA developers. Eventually it will be supported by all members of the members if the alliance where needed.

While large companies like AMD and Nvidia tend to develop their own IP, interconnection, and packaging technologies, multi-chiplet SiPs promise to make the development of complex, chiplet-style processors accessible to smaller companies. For them, standard third-party IP, fast time-to-market, and proper integration are key to success, so 3DFabric Alliance and what it brings will be vital for them.

Source: TSMC

The e-Paper market has enjoyed steady growth over the last decade, starting with the introduction of the Amazon Kindle back in 2007. While there are many vendors attempting to make a mark in the technology required in this space, E-Ink's offerings have ruled the roost.

The most popular category of products using E-Ink's technology has undoubtedly been eBook readers. Recently, digital notebooks and notepads have also emerged as a significant driver in E-Ink's expansion. These products take the regular e-reader and add support for an electronic pen / stylus. These products were initially quite expensive and targeted business professionals dealing with huge amounts of paperwork and requiring note-taking support (such as lawyers). The Sony DPT lineup (review) became one of the leading products in this category. As the market expanded, vendors such as reMarkable and ONYX also started putting out compelling products - expanding the target market to creative professionals and students as well. This category became truly mass-market a few months back with the introduction of Amazon's Kindle Scribe (and slated to start shipping in time for the holiday season).

ONYX has been serving the e-reader market since 2006. They have an extensive lineup of e-readers (both grayscale and color), e-Paper tablets with note-taking support, and even E-Ink monitors. Today, the company is launching a new category - ePaper Tablet PCs. The first product in this lineup is the ONYX BOOX Tab Ultra - a 10.3" unit complete with a 16MP rear-facing camera. A first for E-Ink devices, ONYX envisages the camera being used to OCR documents in the field without the need for an external device as an intermediary. The device targets professional use-cases. It must be noted that ONYX already carries the BOOX Note Air 2 Plus that carries most of the same features, but geared towards the home / casual consumer.

The ONYX BOOX Tab Ultra is the first e-reader model from ONYX to utilize the company's proprietary fast refresh algorithm implemented using a separate hardware module on the board. The company has been using this on its Mira lineup of E-Ink monitors, and its use in the e-reader is supposed to improve user experience with web content. Scrolling, in particular, has been a weak point of E-Ink tablets due to the low refresh rate. The actual improvements delivered by the ONYX 'BSR' (BOOX Super Refresh) algorithm in this aspect needs hands-on evaluation for further analysis. The system supports four different modes for different tasks - reading books doesn't require fast refreshing and can utilize the 'HD Mode', while typing requires a 'Balance Mode'. A 'Fast Mode' is available for web browsing, and an 'Ultrafast Mode' for generic Android applications.

The BOOX Tab Ultra utilizes a Qualcomm Snapdragon 662 SoC (4x Kyro Gold (A73-class) @ 2GHz + 4x Kyro Silver (A53-class) @ 1.8 GHz, along with an Adreon 610 GPU), and comes with a specialized version of Android 11 (including Play Store support). The unit is equipped with a 6300 mAh battery, 4GB of LPDDR4x DRAM, and 128GB of eMMC flash storage. The USB-C port in the system also supports OTG functionality, and a micro-SDXC card slot. A keyboard case with a magnetic holder for the Tab Ultra is also available.

ONYX has a reputation for long support cycles, and provides regular firmware updates to augment the functionality of its ePaper tablets. Recent firmware updates have brought a more tablet-like experience in the user interface - a home screen with apps along with a favorites dock at the bottom. ONYX claims that the use of Android in its tablets (compared to custom OSes in other products such as the Kindle Scribe and reMarkable tablets) enables its customers to take advantage of the host of personal knowledge management apps available for note taking and data collection. Another recently added functionality relates to the association of different pages in different documents using easily-created tags.

The ONYX BOOX Tab Ultra is available for pre-order today and comes with a $600 price tag. The company is also simultaneously releasing the Nova Air 2 7.8" e-Paper tablet with stylus support at $400 and the Leaf 2 7" e-reader at $200. ONYX has typically not hesitated in trying out innovative ideas on the e-Paper front (they were one of the first vendors to bring out color e-readers), and equipping an e-reader / digital notebook with a rear camera is yet another interesting play from the company. The new products expand ONYX's target market and build upon its position as one of the leading E-Ink product vendors in the market in the face of rising competition.

Following on the heels of AMD’s CPU-centric event back in August, AMD today has sent out a press release announcing that they will be holding a similar event in November for their Radeon consumer graphics business. Dubbed “together we advance_gaming”, the presentation is slated to be all about AMD Radeon, with a focus on the upcoming RDNA 3 graphics architecture and all the performance and power efficiency benefits it will bring. The event is set to kick off on November 3^rd at 1pm ET (20:00 UTC), with undisclosed AMD executives presenting details.

Like the Ryzen event in August, next month’s Radeon event appears to be AMD gearing up for the launch of its next generation of consumer products – this time on the GPU side of matters. Back at the start of the summer, AMD confirmed that RDNA 3 architecture products were scheduled to arrive this year, so we have been eagerly awaiting the arrival of AMD’s next generation of video cards.

Though unlike AMD’s CPU efforts, the company has been far more mum about its next-gen GPU efforts. So details in advance on what will presumably be the Radeon RX 7000 series have been limited. The biggest items disclosed thus far are that AMD is targeting another 50% increase in performance-per-watt, and that these new GPUs (Navi 3x) will be made on a 5nm process (undoubtedly TSMC’s). Past that, AMD hasn’t given any guidance on what to expect for performance.

One interesting aspect, however, is that AMD has confirmed that they will be employing chiplets with this generation of products. To what extent, and whether that’s on all parts or just some, remains to be seen. But chiplets are in some respects the holy grail of GPU construction, because they give GPU designers options for scaling up GPUs past today’s die size (reticle) and yield limits. That said, it’s also a holy grail because the immense amount of data that must be passed between different parts of a GPU (on the order of terabytes per second) is very hard to do – and very necessary to do if you want a multi-chip GPU to be able to present itself as a single device.

We’re also apparently in store for some more significant upgrades to AMD’s overall GPU architecture. Though what exactly a “rearchitected compute unit” and “optimized graphics pipeline” fully entail remains to be seen.

Thankfully we should have our answer here in two weeks. The presentation is slated to air on November 29th at 1pm Pacific, on AMD’s YouTube channel. And of course, be sure to check out AnandTech for a full rundown and analysis of AMD’s announcements.

Today marks the release of Intel’s 13th Gen Core series, codenamed Raptor Lake. The first models to be unleashed into retail channels are all overclockable parts, with six SKUs across the Core i9, i7, and i5 product segments. While we’ve seen Intel’s heterogeneous or hybrid design with the launch of Intel’s Alder Lake (12th Gen Core) products, the latest Raptor Lake core brings a very similar design to the table, but with subtle improvements designed to help give Intel the leading edge in the desktop market.

First of these is a ‘new’ Raptor Cove performance (P) core using a refined Intel 7 manufacturing process with some subtle yet critical improvements to the LGA1700 platform to help increase generational performance. Perhaps the most significant benefit comes from adding more efficiency (E) cores, with the flagship SKU, the Core i9-13900K, bringing a total of 24-cores (8P+16E). Which means Intel has effectively doubled the number of efficiency cores on the die.

While there are plenty of talking points, ultimately, the proof, or in this case, performance, is in the pudding. With AMD pulling the trigger on its new Zen 4 core built on TSMC’s 5 nm process, does Intel’s 13th generation Core processors have what it takes to go toe-to-toe with the impressive Ryzen 7000? We aim to discover how Raptor Lake shapes up in our review of the Core i9-13900K and the more affordable Core i5-13600K.

The DisplayPort 2.1 specifications were officially released by VESA on Monday, and this was followed up by USB-IF's announcement of the release of the 80 Gbps USB4 v2 specifications yesterday. These have have brought to fore the significant engineering efforts put into creating a unified protocol capable of handling the external I/O bandwidth requirements of tomorrow's computing systems. Today, Intel is announcing the demonstration of early prototypes for next-generation Thunderbolt based on the USB4 v2 and DisplayPort 2.1 specifications.

Intel's donation of the Thunderbolt 3 specifications to the USB promoters group to form the basis of USB4 has had its share of pros and cons. On one hand, the convergence of the Type-C connector ecosystem theoretically achieved the goal of minimizing end-user confusion, and the royalty-free spec for PCIe tunneling opened up the market to other silicon vendors like ASMedia. However, it also created consumer angst as most of the attractive features of USB4 (such as the 40Gbps bandwidth and compatibility with PCIe tunneling) were entirely optional features. That said, it did enable Intel to market Thunderbolt ports as the Type-C that could do it all. Intel's demonstration of Next Generation Thunderbolt also included a sneak peek into its specifications, even though certain aspects are yet to be finalized. Before delving deeper into Intel's press release, a quick recap of the 80 Gbps USB4 v2 specifications announcement is necessary.

USB4 v2 Updates

USB4 v2 builds upon the multi-protocol tunneling architecture introduced in USB4 by doubling the available bandwidth while maintaining the same port / pins layout and cable structure. This has been achieved by moving the physical layer signal encoding to PAM3 (described in detail in our coverage of 80 Gbps 'Thunderbolt 5' last year). This means that existing 40Gbps USB4 cables will be able to support 80Gbps operation also.

The USB4 v2 specifications now allow tunneling of DisplayPort 2.1 signals and up to four PCIe 4.0 lanes. The data and display protocol updates also make it more efficient, with USB data tunneling capable of exceeding 20 Gbps.

One of the key updates in the move to support DisplayPort 2.1 tunneling relates to the maximum total bandwidth for four lanes in UHBR 20 transmission mode. This translates to 80 Gbps, essentially leaving nothing spare on the transmit side for any other protocol. To handle this, USB4 v2 introduces the concept of asymmetric links. In general, a USB4 link uses two bonded high-speed differential signaling pairs to transmit and receive data, allowing for 40 Gbps duplex operation (40 Gbps transmit and 40 Gbps receive) in the symmetric case. However, the lane initialization process can optionally configure the link to have 3 transmitters and one receiver on one side, and 3 receivers and one transmitter on the other. Combined with the higher data rates thanks to PAM3, this can allow the host to send out 120 Gbps, while lowering the receive bandwidth to 40 Gbps. High-resolution displays can be reliably driven without too much of a sacrifice of the bandwidth available on the transmit side for other purposes (like high-speed storage).

The power delivery specifications have also been updated to match the updates made in USB4 v2, and new logo guidelines have been issued for consumer-facing equipment.

Next-Generation Thunderbolt

Thunderbolt has seen incredible momentum over the last couple of years - triggered mainly by the integration of Thunderbolt controllers inside the high-volume notebook processors starting with Ice Lake. The combination of data, video, and power delivery in one port / cable makes it beneficial to a host of use-cases. In particular, the increasing popularity of hybrid work / hot-desking (monitors / networking etc. behind a dock, allowing multiple employees to just plug in their Thunderbolt-equipped systems at different times) has also served as a fillip to Thunderbolt adoption in the business / office space. Gamers and content creators have an incredible thirst for I/O bandwidth that is served well by Thunderbolt.

As mentioned earlier, Next Generation Thunderbolt takes the USB4 v2 specifications as baseline and makes all of the attractive optional features into mandatory ones. On top of this, Intel's integration of Thunderbolt into the notebook processors ensures that the implementation is power efficient on the host side. Making Thunderbolt mandatory for Intel Evo and vPro notebooks further cements Intel's leadership in the USB4 v2 space.

The dynamic bandwidth rebalancing feature allowing tunneling of the highest bandwidth DisplayPort 2.1 streams while still allowing usage of high-bandwidth peripherals is one of the most exciting features of USB4 v2 that is sure to be available in systems equipped with the Next Generation Thunderbolt ports.

Intel's demonstration included both host and device implementations, with the host configuration shown in the beginning. A discrete GPU's DisplayPort output is fed into the host controller board, and two Type-C cables fork off, one ostensibly to the display, and another to a dock (device) with a SSD attached.

Aspects such as power delivery limits (Thunderbolt 3 / 4 support up to 15W by default) for the Next-Generation Thunderbolt ports will be clarified in the near future. Intel did not provide any information related to market availability.

Based on a glance through the USB4 v2 specifications and Intel's description of Next-Generation Thunderbolt, it is clear that Thunderbolt ports will continue to remain the Type-C port that does it all.

In a short post published on NVIDIA’s website today, the company has announced that it is “unlaunching” their planned GeForce RTX 4080 12GB card. The lowest-end of the initially announce RTX 40 series cards, the RTX 4080 12GB had attracted significant criticism since it’s announcement for bifurcating the 4080 tier between two cards that didn’t even share a common GPU. Seemingly bowing to the pressure of those complaints, NVIDIA has removed the card from their RTX 40 series lineup, as well as cancelling its November launch.

NVIDIA’s brief message reads as follows:

The RTX 4080 12GB is a fantastic graphics card, but it’s not named right. Having two GPUs with the 4080 designation is confusing.

So, we’re pressing the “unlaunch” button on the 4080 12GB. The RTX 4080 16GB is amazing and on track to delight gamers everywhere on November 16th.

If the lines around the block and enthusiasm for the 4090 is any indication, the reception for the 4080 will be awesome.

NVIDIA is not providing any further details about their future plans for the AD104-based video card at this time. However given the circumstances, it’s a reasonable assumption right now that NVIDIA now intends to launch it at a later time, with a different part number.

This is breaking news

As part of this week’s Microsoft Ignite developers conference, Microsoft’s DirectX team has published a few blog posts offering updates on the state of various game development-related projects. The biggest and most interesting of these is an update on DirectStorage, Microsoft’s API for enabling faster game asset loading. In short, the long-awaited 1.1 update, which adds support for GPU asset decompression, is finally on its way, with Microsoft intending to release the API to developers by the end of this year.

In today's review, we are taking a look at the flagship product of Iceberg Thermal, a relatively new US-based company. The IceSLEET G6 Stealth cooler that we are putting to the test today is a behemoth of a CPU cooler, intended to bring quiet cooling to users who want the very best but without the added complexity of liquid-based coolers.

Now that the U.S. government has finally settled the matter of whether it would be providing subsidies to entice chip fabs to setup shop within the U.S., those fabs and chip makers are starting to hammer out their domestic investment plans. Of all of the proposals revealed so far, Micron's new proposal stands to be the most ambitious. Last week the company announced plans to build the largest chip production complex in the history of the U.S. in central New York state. The plan will span 20 years of construction and upgrades, with a total price tag expected to hit around $100 billion by the time Micron is finished in the 2040s. 

Micron's new site near Clay, New York, will not only be the company's largest campus ever built, but will also be the largest chip fab in the USA. The new Micron campus will produce DRAM using leading-edge process technologies and is expected to eventually include four 600,000 feet² (55,700 meters²) clean rooms. Which, to provide some context, is roughly eight-times the clean room space of GlobalFoundries' Fab 8. The new fab complex will complement Micron's already announced campus near Boise, Idaho, that is expected to start coming online starting in 2025. Both sites will be instrumental to meet Micron's goal to produce 40% of its DRAM in the U.S. over the next decade.

According to Micron, the company's investments in its New York production facility will total $100 billion when fully built, and it will create some 9,000 Micron jobs along with some 41,000 indirect jobs. The first phase of the Clay, New York, project is expected to cost Micron around $20 billion in total over the rest of this decade. The DRAM maker expects to get $5.5 billion in incentives from the state of New York over the life of the project, as well as federal grants and tax credits from the CHIPS and Science Act. In addition, Micron and the state of New York will also invest $500 million over the next 20+ years in community and workforce development.

Micron plans to start site preparation work in 2023 and start construction in 2024. The facility ramp up is set to begin in the second half of the decade based on industry demand for DRAM devices.

Broadly speaking, fab complexes with eye-popping price tags are quickly becoming the norm in the fab industry as the cost of building and equipping successive generations of fabs continues to balloon. And while Micron is not the first company to plan for a twelve digit price tag for a new fab complex (Intel's new fab complex in Ohio is officially expected to cost around $100 billion when completed), Micron's announcement is notable in that unlike Intel and TSMC, Micron isn't a logic producer. So the company's $100 billion plans are entirely for memory, a relatively bold commitment for a conservative company that's competing in the tech industry's classic commodity market.

Bearing in mind that the new fab in in Onondaga County, New York, is not set to come online until the later half of the decade, it is too early for Micro to reveal which process technologies and types of products it will produce. The only thing that the company says is that this will be a leading-edge facility that will produce advanced DRAM products (think 64Gb DDR5 chips, DDR6 DRAMs, next-generation HBM, etc.) using EUV-enabled production nodes.

"Micron will leverage the diverse, highly educated and skilled talent in New York as we look to build our workforce in the Empire State," said Sanjay Mehrotra, chief executive of Micron. "This historic leading-edge memory megafab in Central New York will deliver benefits beyond the semiconductor industry by strengthening U.S. technology leadership as well as economic and national security, driving American innovation and competitiveness for decades to come."

Source: Micron

Samsung outlined its foundry business roadmap for the next five years at its Foundry Forum event last week. The company plans to introduce its next generation fabrication technologies in a timely manner and intends to make chips on its 1.4 nm (14 angstroms) manufacturing process by 2027. Also, the company will keep investing in new manufacturing capacity going forward as it strives to strengthen its position in the foundry market.

New Nodes Incoming

Samsung has been introducing new production nodes and/or variants on production nodes every 12 – 18 months for several years now, and plans to keep its rather aggressive pace going forward. Though the company’s roadmap illustrates, fanfare aside, that it is now taking longer to develop new fabrication processes. The company’s second-generation 3 nm-class gate-all-around (3GAP) technology is now set to arrive sometime in 2024. Meanwhile, Samsung Foundry intends to be ready with its 2 nm (20 angstroms) node in 2025, and with its 1.4 nm-branded fabrication process in 2027.

"With the company's success of bringing the latest [3 nm-class] process technology to mass production, Samsung will be further enhancing gate-all-around (GAA) based technology and plans to introduce the 2 nm process in 2025 and 1.4 nm process in 2027," a statement by Samsung reads.

Painting some very broad strokes, compared to those of Intel and TSMC, it seems like TSMC is a little bit more conservative (which is something expected when you are the world's largest contrast maker of microelectronics). Whereas Intel is more aggressive (which is again expected given the company's position in the market of semiconductors). Meanwhile, naming of fabrication processes these days is essentially aspiratory, with little connection to their real physical measures. Which is why comparing different semiconductor companies' roadmaps is an imprecise metric at best.

In addition to new 'general' nodes, Samsung plans to expand its process technology optimization programs for each specific application as well as customized services for customers, the company said.

Meanwhile, one of the things that Samsung notably did not mention in its press release concerning its 1.4 nm node is usage of High-NA equipment. Intel, for its part, plans to use High-NA starting its Intel 18A node (in 2024), where it will eventually be supplanting the EUV multi-patterning used on initial 18A production. 

According to Samsung, the adoption of new process technologies and demand for new fabrication processes will be driven by already known mega trends — AI, autonomous vehicles, automotive applications in general, HPC, 5G, and eventual 6G connectivity. Keeping in mind that Samsung is a large industrial conglomorate with many divisions, many of applications that it intends to address with future process nodes are its own.

The company disclosed last week that its LSI Business (chip development division) currently offers around 900 products, which include SoCs, image sensors, modems, display driver IC (DDI), power management IC (PMIC), and security solutions. Going forward the company plans to put even more efforts into development of performance-demanding IP, including CPU and GPU, by working closer with its industry partners (which presumably includes Arm and AMD).

Expanded Production Capacity

Offering state-of-the-art production technologies is good, but to produce those advanced chips in sufficient quantities to meet market demands is equally important. To that end, Samsung announced that the company will also continue to invest heavily into building out additional production capacity. In the recent years Samsung's semiconductor capacity CapEx was around $30 billion a year and it does not look like the firm plans to put a cap on its spendings (though it is noteworthy that it does not disclose how much money it intends to spend).

Samsung plans to expand its production capacity for its 'advanced' process technologies by more than three-fold by 2027. While the companies is not naming the nodes it considers "advanced", we would expect a significant addition of its EUV capacity in the next five years – especially as more ASML EUV machines become available. Meanwhile, the company will adopt 'Shell-First' tactics in its expansion and construct buildings and clean rooms first, and add equipment later on depending on market conditions.

Samsung's new fab under construction near Taylor, Texas, will be one of the company's main vehicles to add capacity in the coming years. The shell-first site will start to produce chips in 2024. And as the company adds new tools to the fab and build new phases, production capacity of the site will further increase. 

Source: Samsung

Underscoring a difficult second half of the year that seems to be shaping up for the entire tech industry, AMD this afternoon has become the latest tech company to warn investors that revenues for the quarter are going to come in significantly under previous guidance. Releasing a preliminary third quarter financial results statement, AMD is reporting that revenues for the quarter will come in at around $5.6 billion, which is over $1 billion below AMD’s previous guidance of $6.7 billion. Driving this unexpected drop in revenues is an exceptionally weak client market, with revenues down 40% versus Q3’21 and resulting in what’s traditionally AMD’s largest market segment by revenue becoming their smallest.