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A new technical paper, “Rethinking Compute Substrates for 3D-Stacked Near-Memory LLM Decoding: Microarchitecture-Scheduling Co-Design,” was published by researchers at University of Edinburgh, Peking University, University of Cambridge, University of Chinese Academy of Sciences, and the Hong Kong University of Science and Technology.
Abstract
“L...
A new technical paper, “In-SoIC ESD Protection for Chiplet-Based 3D Microsystems: Future Research Directions,” was published by researchers at the University of California, Riverside.
Abstract
“Heterogeneous integration opens a pathway to three-dimensional chiplet-based microsystem chips. Electrostatic discharge reliability is a major challenge ...
A new technical paper, “Epoxy Composites Reinforced with Long Al2O3 Nanowires for Enhanced Thermal Management in Advanced Semiconductor Packaging,” was published by researchers at the Georgia Institute of Technology and National Cheng Kung University.
Abstract
“The rapid increase in heat flux in advanced 2.5D/3D semiconductor packaging places st...
A new technical paper, “Chipmunq: A Fault-Tolerant Compiler for Chiplet Quantum Architectures,” was published by researchers at the Technical University of Munich.
Abstract
“As quantum computing advances toward fault-tolerance through quantum error correction, modular chiplet architectures have emerged to provide the massive qubit counts require...
A new technical paper, “Agentic AI-based Coverage Closure for Formal Verification,” was published by researchers at Infineon and the NIT Jalandhar.
Abstract
“Coverage closure is a critical requirement in Integrated Chip (IC) development process and key metric for verification sign-off. However, traditional exhaustive approaches often fail to ach...