Semiconductor Engineering

The U.S. Commerce Department signed letters of intent for up to $389M in semiconductor R&D funding to four companies working on power devices and ...

At the recent SPIE Photomask Technology + Extreme Ultraviolet Lithography conference, an expert panel discussed the growing importance of edge placement error (EPE). I had the pleasure of joining moderator Jed Rankin of IBM and fellow panelists Hans Stiepan of Carl Zeiss SMT, Ezequiel Vidal-Russell of Micron Technology, Jo Finders of ASML, Il-Yong Jang of Tekscend, and Vivek ...

For decades, silicon characterization has been built around Process, Voltage, and Temperature, or PVT. We characterize devices across process variation, sweep voltage and frequency, control temperature, generate SHMOO plots, and establish the operating envelope of the silicon.

That methodology remains fundamental. But today’s high-performance processors are increasingl...

Key Takeaways:

As their dimensions continue to shrink, conventional gate-all-around (GAA) nanosheet transistors may face growing challenges, such as leakage, mobility, resistance, and manufacturing variability.

A proposed self-aligned complementary field-effect transistor (SA-CFET) architecture addresses these constraints by vertically stacking N-channel metal-oxide-semiconductor (NM...