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Researchers from Yale University, Cornell University, Boston University, and NTT Research have released “Physical Foundation Models: Fixed hardware implementations of large-scale neural networks”.
Abstract
“Foundation models are deep neural networks (such as GPT-5, Gemini~3, and...
The number of defects detected through inspection is exploding at each new process node. There are now millions of defects being identified on each wafer, but only a fraction of those can cause problems. Prasad Bachiraju, senior director of business development at Onto Innovation, talks about the different types of images being captured using different illumination modes at d...
Panel-level packaging, hybrid bonding, new substrates, and fine-pitch interconnects topped the list of advanced packaging technologies at ECTC this week. Among the announcements:
As advanced node SoCs increase in size and complexity, early full-chip DRC runs frequently produce hundreds of millions to billions of violations. This overwhelming scale leads to new challenges—not just in running checks, but in comprehending results, setting priorities, and coordinating closure across teams. Introduced in 2025, Calibre Vision AI enabled instance-complete, A...
Key Takeaways:
Companies can save time and money by swapping out a compute, memory, or I/O chiplet to gain technology improvements, while keeping the other dies stable. Chip architects may choose to keep their I/Os stable and swap out compute to move from a 5nm process node to 3nm to achieve performance and power improvements, o...