Hi all,

Currently encountering some antenna DRCs during layout (TSMC180, analog, manual routing). The error is happening on the M3 layer of some capacitors, as well as the M3 layer of some M1-M4 and M1-M5 stack vias. To my knowledge, antenna DRC errors happen because traces are too long, which can accumulate charge during mfg and potentially blow up the gate oxide. Howe...

Hello,given the following slide shown below as the rise is larger then impedance change in TDR is lower.
Why is that?
the formulas for Zc=1/jwc=-j/(wc) and ZL=jwl
when rise time is faster then the frequency content of the pulse are higher
So inductor impedance is not as capacitor impedance formulas.
What is the frequency domain logic for this rise time issue...

For translinear loop Current conveyor , I had run the simulation and the intrinsic voltage gain and bandwidth response is this. as attached in the picture. Is it normal to have the gain this way? and how can i get the cut off frequency for it ? Since -3dB isnt there. Or if i am doing something wrong please guide me. Thanks

Does anyone use SKILL to draw inductor layout, or some other methods ?

I've seen some literature suggesting using HFSS for electromagnetic simulation first, then exporting it to Virtuoso.

Or use Cadence EMX Planar 3D Solver directly?

Hello everyone
I am designing an axial-mode helical antenna at 1.2 GHz using CST Studio Suite. However, I struggle to achieve the desired S11 (return loss) value. The performance is not as expected despite adjusting parameters such as the number of turns, pitch angle, and ground plane size.

What factors should I focus on to improve the impedance matching and optimi...