Forum for Electronics

The below on page 3-111 decrees that (eg paralleled) SMPS's should be synchronised..

https://www.ti.com/lit/an/slua110/slua110.pdf?ts=1781449769883
However, this is not so, ...as long as each of the FETs' individu...

Rough sawn green sawmill cut “green” Douglas Fir , routered, oiled with 2x8 header 4x6 beam 2.0x6.0 rafters on 24” centers with 36” staggered blocks without purlins and Suntuf polycarbonate roof. 20y old Deck was also drum sanded oiled and clear coated. Winter time just has a heavy duty poly wrap to keep out snow and this 2nd summer added a $25 alumina tarp with acrylic paint un...

Hello ,I have 4 port vna After I calbirate my VNA what is the effect on the s-parameters when the ports are not connected to anything?
Thanks.

Hi,
Supposing you have a 1.6mm thick PCB of 8 layers.
Now suppose there is no board outline clearance, and the copper , including copper planes, on all layers, come right to the board edge. Is there a chance that some of the adjacent layers may suffer shorts between them. (since they are so close together with eg 0.1mm pre-preg only between layers)

Hello , I am testing signal integrity a PCB for 200GEL XDR.
I got some TDR results and SDD21 insertion loss.So I test the impedance value and loss of S21.
How can I know :
1.what is the frequency range ?
2.what levels of SDD21 are suitable?
3.what TDR value that the trace exsibits is proper?
4. Is there some document I could use to answer these questions?...