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Forum for Electronics title: Just a moment...
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Hi all,
I'm developing an IP Core that needs to have a CPU Interface.
The clock from the CPU is around 2 Mhz. (8086)
Can my CPU interface (VHDL) be asynchronous?
I mean, can i use rising_edge of my write signal and falling_edge of my read signal, without any clock?
Thanks.
Hi All
I am designing a Strong Arm Latch ( based on Razavi Paper) . When both the inputs are at the same voltage level , Expectation is that the latch should not be able to take a decision . But the simulation shows output going to HIGH . I am using 1.8V Supply & the common mode voltages are from 500mV to 1600mV. These are not MC sims and hence no mismatch between t...
Hello,
I am writing a question because I have a question while designing an antenna and a voltage doubler on a very thin FPCB.
Originally, the antenna was designed with a CPW structure, but certain GNDs were emptied due to the matching parts.
When I designed it like that, the power needed for ADS simulation was about 4dBm, but in reality, it needed more ...
I tried to solve the above problem. When it is mentioned to make reasonable approximations, i tried to bypass 1MOhm assuming the resistance values are high and little current flows through them. Are my assumptions correct?
As soon as the 2V is dropped all the voltage drops in Rs, I = 2/50k = 0.04mA.
Applying laplace transform
V/s - I(s) * R - I(s)/(C1*s) - I(s)/...
Where does the voltage drop in the below circuit
I am applying the pulsed input of 10V magnitude, before i do the full Laplace transform. I am thinking intutively
Initially the capacitor voltage does not change instantaneously C1 will act like short, C2 also acts like short as per KVL the input voltage Vi has to drop somewhere, where does it drop?
