The Fantastic Four of Linearity Improvement Techniques
Linearity is one of the most, if not THE most, important metric in circuit design. All analog circuits are inherently non-linear mainly because of non-linear behavior of transistors. Many linearity improvement techniques have been discovered or invented in literature yet we only see a few of them in industry practice. This article discusses those few yet fundamental linearity improvement techniques that you must try before you go on with any advance niche solution.
Let’s discuss these techniques in context of V2I converter. A V2I converter or GM cell converts voltage to current, and is usually found in all kind of circuits. For example, it is an essential block in an active mixer based TX as shown in image below. It takes voltage signal from baseband filter (BBF), converts it to current to feed into Gilbert Cell Mixer.
Ok, so say we want to build a linear V2I converter. Let’s start with transistor itself. It’s a natural V2I converter. What’s wrong with it? First off, its g_{m} is a function of signal swing, higher swing leads to higher g_{m}. We want g_{m} to remain fixed over signal swings. Secondly, it does not have any common mode rejection (CMRR). Any variation in DC bias with process or temperature will change the g_{m}. We can resolve this by adding a tail current source. Ok, but how do we fix linearity? We know a resistor is a linear V2I converter, you drop any voltage across it and it produces proportional current (Ohm’s law). It would then be ideal if we could use a resistor for V2I conversion? Yes, but unfortunately there is no direct way we could use a resistor (try to think of a way). First of all, previous stage would need to drive very hard if we put a small resistor, and if we put a big resistor then g_{m} would be pretty low (that would mean its more like a attenuator then amplifier, which is a bummer). Secondly, we need a way of copying current passing through this resistor and feed it to the mixer. It is for latter that we need something more than just a resistor for V2I conversion, and that something more could be a transistor. So that is what folks did. They connected a resistor to a transistor and called it resistive degeneration. The idea is to pass all the voltage at the gate of transistor to the resistor, resistor would convert it to current (which would be very linear), and then transistor can pass that current to the mixer. This works well if the loopgain (g_{m}R) is very very high, otherwise transistor has difficulties passing all the voltage to resistor and drops some voltage across its gate to source (which of course again is function of signal swing, anything with transistor is a function of signal swings really!). But you got some linearity by just using a resistor and transistor, not bad at all. This is where textbook usually stops, and this is where we begin.
There are four basic linearity improvement techniques that are shown in “infographic” below.
Realizing the problem with resistive degeneration was limited loopgain (g_{m}R), one can try to fix it by increasing g_{m} of transistor since we wouldn’t want to change R as it determines our V2I gain. g_{m} can be improved by increasing current of transistor (which is a no no, high current comes with so many issues, not just the power consumption but bigger devices, thicker routing lines, bigger ground bounces, bigger dc offsets, higher noise of bias currents etc.). There are other ways of improving the g_{m}, one of which is called feedback. The idea is to place an opamp before transistor and close the loop on source node of transistor as shown in image below. Opamp would try to force same voltage at its +ive and -ive terminal thereby making the voltage at source node of transistor equal to the input voltage. Voila! this is what we wanted, to pass all the input voltage to resistor. Another way of seeing this is as if transistor g_{m} got boosted by gain of opamp, therefore we also call this linearity improvement technique as g_{m} boosting [4].
Another way of boosting transistor g_{m} is positive feedback. We hear all the time how bad positive feedback it, it make your system oscillate and all that, which is true but its very nature of oscillation (= infinite amplification) can be used to boost g_{m} if employed properly. Caprio’s Quad [3] is one such example as shown in image below. A cross coupled differential pair is introduced between main transistor and degeneration resistor. A cross couple pair has \(\frac{-2}{g_m}\) impedance looking into it which adds to transistor’s g_{m }nulling out the overall g_{m}, and thus variations. Since signal is first fed to main transistor and then feedback happens, this is also called as feedforward linearization.
A more intuitive way of understating it is this: Say M1 received \(V_+\) which increased the current to \(I_+\) while M2 received \(V_-\) which decreased the current to \(I_-\). Now \(I_+\) being higher current would drop higher \(V_{GS}\) across transistor, lets call it \(\Delta V_+\), whereas \(I_-\) would drop smaller \(V_{GS}\), lets call it \(\Delta V_-\). It is the variations of these \(\Delta Vs\) that create signal dependent voltage across resistor. Our goal is to make voltage (\(V_A-V_B\)) across resistor independent of \(\Delta V\) variations which cross couple pair does perfectly by cancelling these variations. Image below shows that \(V_A-V_B\) does not have any \(\Delta V\) when signal traverses the loop (from M1 to M4 to V_{A} to V_{B} to M3 to M2).
The idea of superposition is simple: Add two non-linearities in hope that they cancel each other out. There are different ways this can be accomplished:
Method#1: Say if amplifier A has compressive non-linearity (meaning gain decreases with higher signal) and amplifier B has expansive non-linearity (meaning gain increases with higher signal), A+B would be linear since compression and expansion would compensate each other. Example: take a current source, bias its VDS at its knee point, now any voltage swings at drain of current source would result in expansive current (because swings will take it to triode region where g_{ds} will expand). Add this current to your main amplifier to compensate for its compressive non-linearity.
Method#2: Say amplifier A generates IM3 with some phase \(\phi\), if you could have another amplifier B which generates similar IM3 but with opposite phase \(-\phi\), A+B would be linear. This is not hard to achieve: connect two instances of an amplifier and just bias them at different points, you will already start seeing IM3s subtracting (or adding). Techniques like these are knows as derivative superposition [1].
Method#3: A differential pair g_{m} is very linear right at its bias point but then falls off quickly giving a hump like shape. Good thing is we can move the hump location by setting a different bias point or different device size between +ive and -ive transistor. This means we can take N diff pairs, offset their sizes, add their outputs, and g_{m} would flatten, thus improving linearity. This is shown in image below where two diff pairs are taken. \(V_+\) is given to two transistor with different sizes (one is twice the size of other) and the outputs are added. Total g_{m} can be seen to be flat over wider range of input swings.
If a transistor’s V2I conversion distorts the output by squaring the signal, then same transistor’s I2V distorts the output in an inverse manner (by square-rooting the signal). This means if we cascade I2V and V2I together, the output should be linear. That is precisely what a current mirror accomplishes. You input a current to diode branch, and it gives you perfect replica of it in mirror branch. It takes the current, converts it to voltage (thus pre-distorting it by taking square root of it), that distorted voltage is fed to the mirror branch, and replica current comes out (which is clean of distortion because mirror un-distorts it by taking square of it). This is awesome, however there is a catch: it is current in and current out. We wanted voltage in and current out. We again need help of our friend resistor. We can add an opamp between drain source terminal of diode branch of current mirror as shown in the image below. The idea is to drop the impedance at node x so much that it acts as a virtual ground, this way all voltage provide by \(V_+\) drops across resistor, and current generated flows through diode transistor which is then mirrored to the output transistor. This circuit is noisy and flicker noise can be high, usually current mirror is degenerated to reduce noise transfer function to output (How? Recall why cascode noise is negligible in a cascode amplifier).
[1] Derivative Superposition – Control of Circuit Distortion by Derivative Superposition Method
[2] PreDistortion – The active-input regulated-cascode current mirror
[3] Caprio’s Quad – Precision Voltage to Current Converter
[4] Regulated Cascode (gm boosting) – A high-swing, high-impedance MOS cascode circuit
RFInsights
Published: 30 Jun 2023
Last Edit: 30 Jun 2023
The post Linearity Improvement Techniques appeared first on RFIC Design.
]]>Envelope transient (ET) is a usual method to simulate ACLR with modulated input signals aka waveforms. We simulate circuit performance with same waveforms (little wishful) that we are going to transmit, and whatever ACLR comes out of that, that is it, we optimize ACLR directly with given waveforms. However, during circuit design phase (where we are not even sure what architecture are we going to use), the waveforms might not be ready yet (maybe RFSys team didn’t deliver on time) or running ET simulations might take little too much time. Designers, then, naturally resort back to traditional ways of looking at linearity like harmonics, IM3s and IM5s etc. using Spectre HB. We can simulate ACLR in Spectre HB by emulating waveforms using multi tones excitation. Just like you can excite your circuit with two tones, and simulate IM3, we can excite with multiple tones and simulate ACLR. This way one can proceed on designing the circuit without waiting for or needing actual waveforms, and make circuit architecture choice. Once the circuit is chosen, and its time to go full on optimization, we can start using real waveforms again. This tutorial shows test setup for ACLR simulation in Cadence using multitones.
A sinusoid has 3dB PAPR (peak to average power ratio). For example, 1V sin wave has 0.707V RMS, which means \(\text{PAPR} =20log\left[\frac{1}{0.707}\right]=\text{3dB}\). Two sinusoid waves added together have 6dB PAPR. Four sinusoids have 12dB PAPR, and so on. In general, if N sinusoids are added in-phase the PAPR can be given as:
We make two notes here. First, PAPR is peak to rms ratio in terms of voltage or current (and peak to avg in terms of power, this makes sense since avg power is calculated from rms voltage or current). Second, 20log(N) works when tones are added coherently (in-phase). For example, an OFDM waveform typically has 12dB PAPR even though it is composed of many tones but since they are not in phase, peaks of each tone are unlikely to add, and hence PAPR does not blow up.
Let’s say we want to excite our system with 12dB PAPR. We can use 4 tones in phase, and that would work. A real waveform has many tones in it, therefore we would also like to excite our system with many tones (not just 4) to model our multi tones setup as close to real waveform as possible. Also, we want to distribute energy throughout the band, if we excite our system with just 4 tones, it (non-linearity of our system) will create total 12 IM3 tones (6 falling left to the signal, and 6 falling right), which is something to start with but not much distributed at all. On the other hand, the more the number of tones we inject in system, the longer the HB simulation time. To reduce simulation time, we can excite our system tones that are harmonic multiple of each other. We choose 10 number of tones as a good compromise between simulation time and distribution of energy.
Ok, let’s say we have a TX and we want to excite it with 10 tones with 12dB PAPR. We can choose two tones f_{bb} and f_{bb}_{2}, and excite TX with five harmonics of f_{bb} (i.e., f_{bb}, 2f_{bb}, 3f_{bb}, 4f_{bb}, 5f_{bb}) and five harmonics of f_{bb2} (i.e., f_{bb2}, 2f_{bb2}, 3f_{bb2}, 4f_{bb2}, 5f_{bb2}). This way we will be exciting TX with 10 tones input and only need to enter f_{bb} and f_{bb}_{2 }in HB setup in Cadence (as we will show later). Now how do we generate 12dB PAPR with these 10 tones? We randomize their phases (because we know if they were in phase, PAPR would be 20dB). Here’s the Matlab code that assigns random phases and compute CCDF of 10 tones, such that PAPR is 12dB.
%=== Generate Phases for Given PAPR of 10 Tone Signal ===%
clear all
close all
clc
%Variables
desiredPAPR = 12; %99.9% PAPR you want
angleRange = 90; %confine phases withtin this range (randomly chosen 90, you can choose whatever)
PAPR_99p9 = 0; %init
count = 0; %init
%Define Signal
%Chose t1,t2 such that tones are spread all over the band, meaning f5 and
%f10 should be near the bandedge, not necessary but good to have tones near
%bandedge to estimates WC non-linearity
t1 = 1.91e6;
t2 = 1.87e6;
f1 = 1*t1; phi1=0; %tone 1
f2 = 2*t1; phi2=0; %tone 2
f3 = 3*t1; phi3=0;
f4 = 4*t1; phi4=0;
f5 = 5*t1; phi5=0;
f6 = 1*t2; phi6=0;
f7 = 2*t2; phi7=0;
f8 = 3*t2; phi8=0;
f9 = 4*t2; phi9=0;
f10 = 5*t2; phi10=0; %tone 10
fs = 100*f10; %sampling frequency, lower the better, we chose 100 times of highest frequency f10
stopTime = 1/gcd(t1,t2); %one period of f1+f2+...+f10 -> 1/[GCD of (f1,f2,...,f10)]
%(if f1+f2+...+f10 is even periodic, it might not be always)
t = 0:1/fs:stopTime;
while (PAPR_99p9<0.98*desiredPAPR || PAPR_99p9>1.02*desiredPAPR) && (count<100)
count=count+1;
phi1=round(rand()*angleRange);
phi2=round(rand()*angleRange);
phi3=round(rand()*angleRange);
phi4=round(rand()*angleRange);
phi5=round(rand()*angleRange);
phi6=round(rand()*angleRange);
phi7=round(rand()*angleRange);
phi8=round(rand()*angleRange);
phi9=round(rand()*angleRange);
phi10=round(rand()*angleRange);
y = cos((2*pi*f1*t)+(pi*phi1/180))+...
+cos((2*pi*f2*t)+(pi*phi2/180))+...
+cos((2*pi*f3*t)+(pi*phi3/180))+...
+cos((2*pi*f4*t)+(pi*phi4/180))+...
+cos((2*pi*f5*t)+(pi*phi5/180))+...
+cos((2*pi*f6*t)+(pi*phi6/180))+...
+cos((2*pi*f7*t)+(pi*phi7/180))+...
+cos((2*pi*f8*t)+(pi*phi8/180))+...
+cos((2*pi*f9*t)+(pi*phi9/180))+...
+cos((2*pi*f10*t)+(pi*phi10/180));
%Calculate CCDF of Signal y
CDF = histogram(20*log10(abs(y)/rms(y)),1000000,'Normalization','cdf','Visible','off');
CCDF_y = 100*(1-CDF.Values);
CCDF_x = CDF.BinEdges;
index_99p9=find(CCDF_y<100-99.89 & CCDF_y>100-99.91);
PAPR_99p9 = CCDF_x(index_99p9(1));
phases = [phi1 phi2 phi3 phi4 phi5 phi6 phi7 phi8 phi9 phi10];
fprintf('Count %d PAPR %0.3f with Tone Phases %d %d %d %d %d %d %d %d %d %d\n',count,PAPR_99p9,phases);
end
%Plot CCDF
semilogy(CCDF_x(2:end),CCDF_y,'LineWidth',3); %to make vectors lenght same, started from index 2 of CCDF_x,
%removes very low value data, thats ok
%Format Plots
ax = gca;
ax.FontSize = 12;
ax.FontName = 'Arial';
ax.TickDir = 'in';
ax.TickLength = [0.02 0.02];
ax.YGrid = 'on';
ax.XGrid = 'on';
ax.LineWidth = 2;
ax.XLim = [-5 15];
ax.YLim = [0.001 100];
ax.XTick = [-15:1:15];
xlabel('PAPR [dB]');
ylabel('CCDF [%]');
%Print PAPR
index_99p99=find(CCDF_y<100-99.989 & CCDF_y>100-99.991);
index_99p9=find(CCDF_y<100-99.89 & CCDF_y>100-99.91);
index_99p=find(CCDF_y<100-98.9 & CCDF_y>100-99.1);
index_50p=find(CCDF_y<100-49.8 & CCDF_y>100-50.1);
PAPR_100p = 20*log10(max(abs(y))/rms(y));
PAPR_99p99 = CCDF_x(index_99p99(1));
PAPR_99p9 = CCDF_x(index_99p9(1));
PAPR_99 = CCDF_x(index_99p(1));
PAPR_50 = CCDF_x(index_50p(1));
if count==100
fprintf(2,'*****Failed to Achieve PAPR***\n',rms(y))
else
fprintf(1,'********PAPR Achieved********\n',rms(y))
fprintf(2,'RMS of Signal = %.3f V\n',rms(y))
fprintf(2,'100%% PAPR of Signal = %.3f dB\n',PAPR_100p)
%fprintf(2,'99.99%% PAPR of Signal = %.3f dB\n',PAPR_99p99)
fprintf(2,'99.9%% PAPR of Signal = %.3f dB\n',PAPR_99p9)
fprintf(2,'99%% PAPR of Signal = %.3f dB\n',PAPR_99)
fprintf(2,'50%% PAPR of Signal = %.3f dB\n',PAPR_50)
fprintf(2,'with these tone phases in degree [%d %d %d %d %d %d %d %d %d %d]\n',phases)
fprintf(1,'*************Done*************\n',rms(y))
end
When we ran this code in Matlab, it generated following output:
It says, I assigned random phases to 10 tones, computed CCDF and got 99.9% PAPR which was 10.7dB, it did not meet our target of 12dB (which is set by desiredPAPR vairable in code). It kept trying and at 6^{th} attempt, the phases came out such that PAPR target is met, and it reports those phases to be [54 35 13 2 38 17 65 33 76 66] degree for [f_{bb }2f_{bb} 3f_{bb} 4f_{bb} 5f_{bb} f_{bb}_{2} 2f_{bb}_{2} 3f_{bb}_{2} 4f_{bb}_{2} 5f_{bb2}] respectively. What is CCDF and 99.9% PAPR? See appendix.
Our matlab code gave us phases for 10 tones. The code was written with cosines which means I channel signal. If we were to use the same phases for sines (i.e., Q channel) what PAPR would we get? and when IQ are combined by TX, what would be the PAPR then? Let’s check that before we go for ACLR simulation in Cadence. Here’s Matlab code for that:
%=== Estimate CCDF of I and Q signal ===%
clear all
close all
clc
%Colors
red = [233 30 86]/255;
green = [64 206 127]/255;
yellow = [254 219 57]/255;
blue = [87 172 220]/255;
grey = [63 63 63]/255;
wbg = [19 20 23]/255;
white= [1 1 1];
orange = [231 76 60]/255;
purple = [144 43 245]/255;
figure1 = figure('Color',wbg);
%Define Signal
t1 = 1.91e6;
t2 = 1.87e6;
f1 = 1*t1; phi1=54; %tone 1
f2 = 2*t1; phi2=35; %tone 2
f3 = 3*t1; phi3=13;
f4 = 4*t1; phi4=2;
f5 = 5*t1; phi5=38;
f6 = 1*t2; phi6=17;
f7 = 2*t2; phi7=65;
f8 = 3*t2; phi8=33;
f9 = 4*t2; phi9=76;
f10 = 5*t2; phi10=66; %tone 10
fs = 100*f10; %sampling frequency, higher the better, we chose 100 times of highest frequency f10
stopTime = 1/gcd(t1,t2); %one period of f1+f2+...+f10 -> 1/[GCD of (f1,f2,...,f10)]
%(if f1+f2+...+f10 is even periodic, it might not be always)
t = 0:1/fs:stopTime;
y1 = cos((2*pi*f1*t)+(pi*phi1/180))+...
+cos((2*pi*f2*t)+(pi*phi2/180))+...
+cos((2*pi*f3*t)+(pi*phi3/180))+...
+cos((2*pi*f4*t)+(pi*phi4/180))+...
+cos((2*pi*f5*t)+(pi*phi5/180))+...
+cos((2*pi*f6*t)+(pi*phi6/180))+...
+cos((2*pi*f7*t)+(pi*phi7/180))+...
+cos((2*pi*f8*t)+(pi*phi8/180))+...
+cos((2*pi*f9*t)+(pi*phi9/180))+...
+cos((2*pi*f10*t)+(pi*phi10/180));
y2 = sin((2*pi*f1*t)+(pi*phi1/180))+...%+ive sin because we want f1-f5 to convert to LSB
+sin((2*pi*f2*t)+(pi*phi2/180))+...
+sin((2*pi*f3*t)+(pi*phi3/180))+...
+sin((2*pi*f4*t)+(pi*phi4/180))+...
+sin((2*pi*f5*t)+(pi*phi5/180))+...
-sin((2*pi*f6*t)+(pi*phi6/180))+... %-ive sin because we want f6-f10 to convert to USB
-sin((2*pi*f7*t)+(pi*phi7/180))+...
-sin((2*pi*f8*t)+(pi*phi8/180))+...
-sin((2*pi*f9*t)+(pi*phi9/180))+...
-sin((2*pi*f10*t)+(pi*phi10/180));
y3 = y1+y2; %IQ Combined
%Calculate CCDF of Signal y1 & y2
CDF_y1 = histogram(20*log10(abs(y1)/rms(y1)),1000000,'Normalization','cdf','Visible','off');
CCDF_y1_y = 100*(1-CDF_y1.Values);
CCDF_y1_x = CDF_y1.BinEdges;
CDF_y2 = histogram(20*log10(abs(y2)/rms(y2)),1000000,'Normalization','cdf','Visible','off');
CCDF_y2_y = 100*(1-CDF_y2.Values);
CCDF_y2_x = CDF_y2.BinEdges;
CDF_y3 = histogram(20*log10(abs(y3)/rms(y3)),1000000,'Normalization','cdf','Visible','off');
CCDF_y3_y = 100*(1-CDF_y3.Values);
CCDF_y3_x = CDF_y3.BinEdges;
%Plot CCDF
semilogy(CCDF_y1_x(2:end),CCDF_y1_y,'LineWidth',3,'Color',green); %to make vectors lenght same,
%started from index 2 of CCDF_x, removes very low value data, thats ok
hold on
semilogy(CCDF_y2_x(2:end),CCDF_y2_y,'LineWidth',3,'Color',red);
hold on
semilogy(CCDF_y3_x(2:end),CCDF_y3_y,'LineWidth',3,'Color',yellow);
%Format Plots
ax = gca;
ax.FontSize = 14;
ax.FontName = 'Arial';
ax.TickDir = 'in';
ax.TickLength = [0.02 0.02];
ax.YGrid = 'on';
ax.XGrid = 'on';
ax.LineWidth = 2;
ax.XLim = [-5 15];
ax.YLim = [0.001 100];
ax.XTick = [-15:1:15];
xlabel('PAPR [dB]','Color',white),ylabel('CCDF [%]','Color',white)
ax.Color=wbg;
ax.XColor=white;
ax.YColor=white;
ax.GridColor=white;
ax.MinorGridColor=white;
l=legend('I CH','Q CH','IQ Combined');
l.Color=wbg;
l.TextColor=white;
%Print PAPR I
index_99p99=find(CCDF_y1_y<100-99.989 & CCDF_y1_y>100-99.991);
index_99p9=find(CCDF_y1_y<100-99.89 & CCDF_y1_y>100-99.91);
index_99p=find(CCDF_y1_y<100-98.9 & CCDF_y1_y>100-99.1);
index_50p=find(CCDF_y1_y<100-49.8 & CCDF_y1_y>100-50.1);
PAPR_100p = 20*log10(max(abs(y1))/rms(y1));
PAPR_99p99 = CCDF_y1_x(index_99p99(1));
PAPR_99p9 = CCDF_y1_x(index_99p9(1));
PAPR_99 = CCDF_y1_x(index_99p(1));
PAPR_50 = CCDF_y1_x(index_50p(1));
fprintf(1,'***CCDF Properties of I Signal*************\n',rms(y1))
fprintf(2,'RMS of Signal = %.3f V\n',rms(y1))
fprintf(2,'100%% PAPR of Signal = %.3f dB\n',PAPR_100p)
fprintf(2,'99.99%% PAPR of Signal = %.3f dB\n',PAPR_99p99)
fprintf(2,'99.9%% PAPR of Signal = %.3f dB\n',PAPR_99p9)
fprintf(2,'99%% PAPR of Signal = %.3f dB\n',PAPR_99)
fprintf(2,'50%% PAPR of Signal = %.3f dB\n',PAPR_50)
%Print PAPR Q
index_99p99=find(CCDF_y2_y<100-99.989 & CCDF_y2_y>100-99.991);
index_99p9=find(CCDF_y2_y<100-99.89 & CCDF_y2_y>100-99.91);
index_99p=find(CCDF_y2_y<100-98.9 & CCDF_y2_y>100-99.1);
index_50p=find(CCDF_y2_y<100-49.8 & CCDF_y2_y>100-50.1);
PAPR_100p = 20*log10(max(abs(y2))/rms(y2));
PAPR_99p99 = CCDF_y2_x(index_99p99(1));
PAPR_99p9 = CCDF_y2_x(index_99p9(1));
PAPR_99 = CCDF_y2_x(index_99p(1));
PAPR_50 = CCDF_y2_x(index_50p(1));
fprintf(1,'***CCDF Properties of Q Signal*************\n',rms(y1))
fprintf(2,'RMS of Signal = %.3f V\n',rms(y1))
fprintf(2,'100%% PAPR of Signal = %.3f dB\n',PAPR_100p)
fprintf(2,'99.99%% PAPR of Signal = %.3f dB\n',PAPR_99p99)
fprintf(2,'99.9%% PAPR of Signal = %.3f dB\n',PAPR_99p9)
fprintf(2,'99%% PAPR of Signal = %.3f dB\n',PAPR_99)
fprintf(2,'50%% PAPR of Signal = %.3f dB\n',PAPR_50)
%Print PAPR IQ
index_99p99=find(CCDF_y3_y<100-99.989 & CCDF_y3_y>100-99.991);
index_99p9=find(CCDF_y3_y<100-99.89 & CCDF_y3_y>100-99.91);
index_99p=find(CCDF_y3_y<100-98.9 & CCDF_y3_y>100-99.1);
index_50p=find(CCDF_y3_y<100-49.8 & CCDF_y3_y>100-50.1);
PAPR_100p = 20*log10(max(abs(y3))/rms(y3));
PAPR_99p99 = CCDF_y3_x(index_99p99(1));
PAPR_99p9 = CCDF_y3_x(index_99p9(1));
PAPR_99 = CCDF_y3_x(index_99p(1));
PAPR_50 = CCDF_y3_x(index_50p(1));
fprintf(1,'***CCDF Properties of IQ Combined Signal***\n',rms(y1))
fprintf(2,'RMS of Signal = %.3f V\n',rms(y1))
fprintf(2,'100%% PAPR of Signal = %.3f dB\n',PAPR_100p)
fprintf(2,'99.99%% PAPR of Signal = %.3f dB\n',PAPR_99p99)
fprintf(2,'99.9%% PAPR of Signal = %.3f dB\n',PAPR_99p9)
fprintf(2,'99%% PAPR of Signal = %.3f dB\n',PAPR_99)
fprintf(2,'50%% PAPR of Signal = %.3f dB\n',PAPR_50)
Above code will generate following output:
We can see the CCDF properties of I channel are what we designed for (i.e., 99.9% PAPR is ~12dB). However, Q channel 99.9% PAPR is 10.6dB (about 1.5dB short of 12dB target). Same phases for sines and cosines will not get us same PAPR. We can re-run the first matlab code, and get another set of phases, and try it to see if I and Q PAPR are any closer or we can increase number of tones to resolve this. It’s also interesting to see what I+Q PAPR would be when they eventually get combined. Statistically, I+Q PAPR is 3dB less than I and Q PAPR because rms adds but chances for peaks to be aligned are slim, I and Q peak would unlikely to occur at same time, hence peaks won’t add, thus reducing PAPR. However, sometimes they do add and PAPR of I+Q is similar to I or Q PAPR or even higher. For our 10 tones with the phases chosen, I+Q PAPR happens to be similar to I PAPR as shown in image below.
Let’s now use 10 tones, with phases we obtained above, in Cadence Virtuoso and see if it CCDF and PAPR matches our calculations in Matlab. Figure below shows Cadence schematic and setup of multiple tones. We used analogLib/isin current sources. Since they are sine signals by default, we added 90 degree to all of them to make them cosine, and then we added phases to them shown as phi1 and phi2 for the first current source (I108). Similarly, rest of the 4 current sources contain rest of the 8 tones with phases (not shown in image). For Q channel, we added the same phases (however without extra 90 degree now, since we want sine signals now). Since we wanted to distributed tones evenly throughout the band, therefore we placed f_{bb}_{2} and its harmonics to upconvert to right side of LO (USB upconversion, LO+f_{bb}_{2}) by assigning -ive polarity to amplitude; and f_{bb} tones to upconvert to left side of LO (LSB upconversion, LO-f_{bb}) by assigning +ive polarity to amplitude. This way LO will be at center and we will have 5 tones upconverted to the right side of LO and 5 tones to the left side, symmetrically occupying bandwidth around LO.
We used histogram2D function in Cadence calculator to plot CDF of signal, then we subtract it from 1 to make it CCDF. A factor of 1e-07 is added to avoid zero signal amplitude because in dB this destroys the scale and ruins the quantization for histogram. We use 1000000 bins for histogram. The higher, the better (but it takes long time to calculate then). We used strobe period of \(\frac{1}{100f}\) where f is the highest frequency in the system. The lower the strobe period, the better but again it takes long to calculate then. We simulate for one time period which is usually \(\frac{1}{\text{GCD of [f1+f2+…+f10]}}\). We said usually because the sum might not be periodic all the time, if your [f1+f2+…+f10] is not periodic, your best bet is to simulate long enough such that you capture all the peaks. We used abSortXValues function in Cadence to help with plotting (it converts bins to points, and cadence can then interpolate between them to sketch a plot). Please look at image above to figure out how did we define everything else. For example, you can see N that we used in expression below is defined in design variables as \(\frac{\text{tstop}}{\text{ts}}\).
abSortXValues((100 * (1 - (histogram2D(dB20(((v_signal_i_norm + 1e-07) / v_signal_i_norm_rms)) 1000000 "cumulative box" nil nil) / N))))
Simulations match quite well with Matlab calculations. For example, 99.9% PAPR of I channel in Cadence is 12.02dB whereas it is 11.99dB in Matlab. Spot on! (Little bit difference in fractions come from finite sampling frequency and finite number of histogram bins if you cared that much). Similarly, PAPR of Q or I+Q are also very close to Matlab calculations. This means that our setup in Cadence is good and Cadence & Matlab correlate. We can compute phases in Matlab and be sure that it will give us the PAPR in Cadence as Matlab calculated.
CCDF curves between Cadence and Matlab also match pretty well.
Let’s now use 10 tones to simulate ACLR in Cadence. Say our TX is operating with 20MHz bandwidth in the first chunk of LTE Band 1 (i.e., 1920MHz to 1940MHz with LO at 1930MHz). Say we have a guardband (GB) of 0.4525MHz. GB is a no man’s land, no one can transmit in GB, each channel has to give up 2GB space, one to the left edge of the band and one to the right edge of the band, this way we have 2GB space between signal edge and adjacent channel edge, as shown in image below.
We have 10MHz available to the left of LO and 10MHz to the right of LO. To evenly distribute the tones, let’s choose f_{bb} to be 1.91MHz so that 5f_{bb }is 9.55MHz which is ~bandedge (10MHz – GB). We place these tones to the left side of LO by choosing +ive polarity of amplitudes in Q-channel current sources as explained before. Let’s choose f_{bb2} to be 1.89MHz so that 5f_{bb2 }is 9.45MHz which is ~bandedge (10MHz – GB). We place these tones to the right side of LO by choosing -ive polarity of amplitudes in Q-channel current sources.
We used ideal blocks in Cadence to build IQ TX with non-linearity as shown below. IQ TX is excited with 10 tones signals with phases we chose before, and our goal it to measure ACLR at the output of RF amplifier.
We plot the power across output resistor, and it comes out as a spectrum. It’s hard to deal with Spectrum data in Cadence, so we used some custom built functions which are attached below. Here’s what they do:
abSumValues(abs(awvcClipNoExtrapolate(abSortXValues(pvi('hb "/v_iq_post_amp" "/gnd!" "/R6/PLUS" 0)) 1.92045e+09 1.93955e+09)))
Note: These functions are not written by us. These are provided by Cadence Community for its customers. Save them with .il extension, and use 'fx' button in calculator to add them.
Simulated results are shown below. We can see we have LO tone at 1930MHz, there are 5 signal tones to the right and 5 to the left side of it. Rest of the tones are distortion products and they look much like as if were an ACLR plot from modulated signals. Mission accomplished.
Image below show ACLR to be 65dBc (or -65dBc if you like negative sign) for -12dBm of output power.
This concludes our tutorial on how to generate a waveform with desired PAPR using multitones and set them up in Cadence to simulate ACLR.
PAPR is a very critical metric for system and circuit designers alike. The waveforms that we excite our systems with are statistical in nature, and we want to know what is the probability that peak will occur. We measure this with CCDF (\(P(x \geq X)\)) of waveform. For example, if we say PAPR is 9dB, we want to know what are the chances our signal will actually have 9dB PAPR (is it just one time thing, or is peak occurring after every 10 samples of signal or after 100 samples?). Image below shows a CCDF plot, we can see for 10T signal (red curve), the probability of PAPR 9dB or higher is 1% or the probability that PAPR will never exceed 9dB is 99%. Thus, we will say 99% PAPR of this waveform is 9dB. We also plotted CCDF of AWGN for fun. We can see 99% PAPR for AWGN is about 8.2dB. Typically, we use 99.9%, 99.99% and 100% to communicate PAPR numbers between design teams.
RFInsights
Published: 24 Jun 2023
Last Edit: 24 Jun 2023
The post ACLR Simulation in Cadence appeared first on RFIC Design.
]]>Time to time, debugging or modelling a circuit, we look for ideal blocks in Cadence that can do the job, prove the concept before you go on fully developing the thing. We heard you. Here are some ideal blocks that are already available in Cadence Virtuoso libraries that you can get started from.
Cadence library: ahdlLib/adder
Example use case: Adder can be used for adding signals, for example, if you want to add I and Q signal to generate 45 deg signal.
Cadence library: ahdlLib/subtractor
Example use case: Subtractor can be used when you want to take difference of signals, for example, differential to single ended conversion
Cadence library: ahdlLib/multiplier
Example use case: Multiplier can be used when you want to multiply two signals, for example, you can use it as a mixer. A mixer is an multiplier ideally. You can multiply baseband and LO signal, and at output you should see LO+BB and LO-BB signal.
Cadence library: ahdlLib/amp
Example use case: when you want to scale your signal (amplify or attenuate)
Cadence library: analogLib/delay
Example use case: Adding a delay to signal, for example, you can generate Q signal from I by adding a T/4 delay to it.
Cadence library: analogLib/delayline
Example use case: This blocks also adds a delay and has a characteristic impedance. For example, it can act as an ideal transmission line with some delay.
Cadence library: analogLib/delay
Example use case: We can repurpose delay block to act as a phase shifter. For example, if you want to add phase delay of \(\phi\) at frequency f, you can add \(\dfrac{\phi}{2\pi f}\) delay.
This adds phase delay/lag only, phase advance/lead is not possible with this. To add phase lead, you can add delay to your reference. (afterall you added phase delay wrt some reference, so find that reference, and add delay to it, it will be as if you added phase lead to your intended signal)
Cadence library: rfLib/LNA_PB
Example use case: We can add distortion and noise using this block. For example, if you want excite your power amplifier with some already distorted signal (signal+IM3).
Cadence library: ahdlLib/polynomial
Example use case: This is a very useful block. If you only want to inject particular non-linearity, say only second order harmonics, you can use this block to set the coefficients of polynomial. For example, if you set p3 to zero in image below, it will only create 2nd order non-linearity.
There are many other blocks to be explored in analogLib, ahdlLib and rfLib libraries. For example, you can insert bandpass ideal filters from rfLib/butterworth_bp. We already have a dedicated article on ideal low pass filters. You can use ahdlLib/diffamp as opamp.
This is an extremely useful probe. Sometimes you want to attach something to a node (say for debugging purposes, you want to attach a capacitor to rdegen node shown in image below) that is buried deep in hierarchy, and ripping up that hierarchy or bringing a pin out just for this is way too much work. In this case, you can use analogLib/deepprobe to access that node anywhere in your top level cell.
For example, say we want to access vp node as shown image below. We would insert a deepprobe at top level schematic, and write gm.ich.rdgn.vp (syntax: cell instance name. cell instance name…node name) in its hierarchical node property. This will get us access to the node, and now we can connect whatever we want to this node (like we connected a capacitor in this case).
RFInsights
Published: 16 Jun 2023
Last Edit: 16 Jun 2023
The post Ideal Blocks in Cadence appeared first on RFIC Design.
]]>The output of a power amplifier (PA) is terminated with a specific impedance. This impedance is required for optimal linearity or power generation or efficiency or combination of such specs, and is determined by loadpull analysis. We call it loadline. While a loadline helps PA deliver its performance, the matching (VSWR) gets ruined because we do not present conjugate load to PA. Typically, we insert a circulator between antenna and PA such that reflections don’t reach back to PA, and get absorbed in port 3 of circulator as shown in image below.
This works fine for front-end modules where off-the-shelves blocks can be patched together to curb the ailment. In context of TX RFIC where adding an circulator might not be possible (as they are made of ferrite), we discuss how loadline can be designed while also meeting the VSWR requirements.
Say we have a TX with output resistance R_{o} and output capacitance C_{o}. We have a requirement to present a certain resistance R_{LL} to this TX, and also maintain certain VSWR looking from 50\(\Omega\) port. TX is differential, so we also want to convert it to single ended while doing so. Our job is to figure out how should the white box be designed.
One of the ways we can accomplish this is shown in image below. First, we add a balun to convert differential to single ended. Second, we add a resistor R_{M} to introduce loss into system as we will see later that simultaneous R_{LL} and VSWR requirements cannot be satisfied without adding R_{M} (also see a note on similar topic in appendix). We also add a capacitor C_{T} at primary of balun to tune out primary inductance partially, and C_{L} at secondary to tune out leftover inductance. (We mentioned tuning out primary inductance but not secondary – because there is only one inductance to tune out, the other inductance is a leakage inductance L_{K} which is very small or zero if coupling coefficient is one, see transformer model # 4). One can just use C_{T} or C_{L} to tune out, we distributed the cap because it gives us a knob for loss optimization (more on this later). Our goal is to find R_{L} and C_{L} such that both R_{LL} and VSWR are satisfied. Note R_{L} is not a physical resistor, it the resistance value to which we want our 50\(\Omega\) port to convert to.
Let’s put some numbers in. Say we have 5k\(\Omega\) R_{o} and 100fF C_{o}. We have C_{T}, R_{M}, L_{p}, L_{s}, k, Q_{p}, Q_{s} at our disposal to optimize. We start with 5nH L_{p}. It’s just a guess, you can use any L_{p}, things you would need to consider in choosing L_{p} are:
L_{s} is usually chosen to be 0.707 or 1.414 of L_{p} because this aspect ratio usually gives the highest k. Let’s make R_{M} infinite for now, and choose a random value of C_{T}, and begin! First, let us find what values of resistance and reactance do we need looking into primary of balun, that would get us desired loadline. Let’s call them R_{x} and X_{x}. We believe an analytical solution maybe worked out but we went with iterative solution in Microsoft Excel. We assume some initial value of R_{x} and C_{x}, and start simplifying the circuit till we get to R_{e} and X_{e}. This is shown in image to the right starting from top and ending at bottom. Excel would keep iterating different values of R_{x} and X_{x} until it gets us \(R_e=R_{LL}\) and \(X_e=\infty\), which is what we would want to see pure R_{LL}.
Once we have found R_{x} and X_{x} needed at primary, we can multiply it by turn ratio square and figure out an equivalent RX needed at secondary. We then move this RX step by step towards the output, and finally arrive at R_{L} and C_{L} values. Basically this would mean: attach a C_{L} capacitor at output node, and attach a matching network that transforms port 50\(\Omega\) to R_{L}. If done, your R_{L }C_{L} would transform through balun parasitics and other components we added, and once they make it to TX current source, all the imaginary part would have been stripped off and you should see real R_{LL}.
(Note it is also possible that your matching network transforms port 50\(\Omega\) to R_{L} || X_{L} directly, so one can remove C_{L})
We built an Excel calculator which details these calculations. Different parameters we assumed are in oranges boxes and R_{L} C_{L} values under Final Results. Our goal was 60\(\Omega\) R_{LL}, and our calculator says we need to have \(R_L=50.8\Omega\) and \(C_L=1762.3fF\) to achieve this R_{LL}. Ok great, how about VSWR though? Our Excel sheet does similar calculations for VSWR and shows that we need \(R_L=598.1\Omega\) and \(C_L=453.9fF\) to get 1:1 VSWR. This R_{L} C_{L} is way way off from what we need for R_{LL}. This is not surprising as VSWR is simplify looking for conjugate load which happens to be very different from our desired R_{LL}. In other words, if had just gone for conjugate match for TX output, our VSWR would have been perfect but we would not have gotten the R_{LL }we wanted.
How can we remedy this situation where we have different R_{L} C_{L} values to meet given R_{LL }and VSWR? By adding R_{M}. See that our loss in image above is 1.66dB, once we add R_{M} we can tradeoff loss with VSWR. Let’s set our VSWR target to 1:1.5. By playing with R_{M }and C_{T }(of course you can play with other variables too, everything is on the table) we can arrive at R_{L} C_{L} values which will give the R_{LL} we want while meeting the VSWR. Image below shows that we don’t need different value of C_{L }now, and R_{L }are still somewhat different but they meet VSWR condition. You can make R_{L }values similar too by reducing R_{M} at the expense of more loss. We are already hitting 3.86dB loss to get 1.5 VSWR. Our finally R_{L} and C_{L }are 49.7\(\Omega\) and 587fF.
Now one might ask that role of R_{M }is clear, but what do we need C_{T }for. Can we get rid of C_{T }and just use C_{L} to tune out balun? The answer is yes but at the expense of slightly higher loss (not always though, devil lies in details, one need to analyze the particular situation). C_{T }was placed strategically. Ideally, we should tune out things where they emerge, meaning we should have tuned L_{p }right where it was (at primary). If we don’t tune it here, and instead try to get the -ive reactive part all the way from C_{L}, it will go through impedance transformations at different nodes (as shown in images above) and at some node if Q is high, it will result in higher loss. How do you know at which node Q is high? You can lookup the Q of all the nodes in our Excel calculator, it’s colored sky blue.
Another question one might ask is if loss gets us VSWR, can we get rid of R_{M }and instead make our balun intentionally lossy (i.e., lower Q)? The answer is not really. It turns out series and shunt losses are different. A series resistor creates two nodes in the circuit and hence creates asymmetry in left and right impedances. For example, if you see that optimum of VSWR and R_{L}_{L} don’t align in frequency that is maybe you got optimum R_{L}_{L} at 2.4GHz but optimum VSWR at 2.5GHz, know that this is because of series resistor somewhere. A shunt resistor keeps this symmetry. Since inductor’s loss is physically a series resistor, we always want to maximize Q to reduce this resistor. Also there are other benefits of putting R_{M} (as shown in our circuit, center of R_{M} goes to supply, we intentionally made it a common mode), this helps in providing even harmonics a path to ground. Otherwise, they will be forced to find a way to circulate in your circuit and create non-linearities you wouldn’t have imagined (like weird combinations of mixing products with your signal, that will land back at your IM3s/5s for example).
Let’s now head to Cadence and plug our numbers in to see if our methodology works. Cadence schematic is shown below. Note that there is no explicit L_{K} here because that was just for our math, real L_{K} is modelled by finite k which we have added in our circuit using “mind” instance in analogLib. Also note that there are two circuits shown but they are exactly the same, just different excitations: one measures R_{L}_{L} and other measures VSWR.
Image below shows simulation results. R_{L}_{L}, VSWR and loss are match pretty well with our calculations.
Excel calculator is attached below. One can start with this calculator to gain insights into circuit (like where is loss coming from, what variable does what, and which variable needs tight control in terms of design sensitivity) and later move on to directly optimization in Cadence.
A subtle difference between mm-wave and RF impedance matching: at mm-wave, transistor output already contains low resistive part (either with existing losses in the circuit or through numerous feedback paths between output and different nodes of circuit that eventually introduce real part in output impedance), therefore one can just go on matching port to transistor output impedance. At RF, real part of output impedance is quite high (almost an open circuit) making it impossible to match to 50\(\Omega\\) because matching network requires very high Q which makes matching very sensitive and low bandwidth. Therefore, we intentionally add a resistor to introduce real part, making things low Q and match-worthy.
(One can think of ways of adding a real part to transistor output impedance without adding resistor itself and that would work too)
RFInsights
Published: 14 Jun 2023
Last Edit: 14 Jun 2023
The post Loadline Design appeared first on RFIC Design.
]]>Residual sideband suppression (RSB) is one of key TX specs. We want to minimize this because this degrades EVM (when LO is centered to CC leading to signal and its image falling on top of each other) or degrades ACLR (when LO is not centered to CC leading to different signal and image locations). Mismatches in amplitude or phase of I and Q channels in IQ TX generate RSB. Therefore, IQ correction is a usual calibration routine that is followed in industry practice where IQ errors are measured and corrected. We discuss below how it is done in context of TX.
Consider an ideal IQ TX. I channel receives a cosine baseband signal from DAC and multiplies it with cosine LO. Q channel receives a sin baseband signal from DAC and multiplies with sin LO. Multiplication generates two sidebands: \(\omega_{LO}+\omega_{BB}\) aka upper sideband (USB) and \(\omega_{LO}-\omega_{BB}\) aka lower sideband (LSB). When I and Q are summed, one of the sideband cancels. Depending on the sign of “isLSB” (shown in image below), either lower sideband or upper sideband is transmitted, and the one that is cancelled is then called as residual sideband or image. The ratio of residual sideband to transmitted sideband is called as image rejection ratio (IRR). IRR is infinite in an ideal TX with no IQ mismatch.
Let \(\large \textcolor{#FEDB39}{\epsilon}\)\( \; \& \; \textcolor{#FEDB39}{\varphi} \) be the gain and phase mismatch (in radians) between I and Q channels. We can either scale I channel or Q channel to represent gain mismatch. Similarly, we can either add phase shift in I channel or Q channel (LO path or BB path) to represent phase error. The outcome is going to be the same i.e., a given gain and phase mismatch would give a certain RSB no matter where it comes from. Let’s scale the I-channel and add phase shift in Q LO path as shown in image below.
We can write output as follows:
where \(\Sigma = (\omega_{LO}+\omega_{BB})t\) and \(\Delta = (\omega_{LO}-\omega_{BB})t\)
Let’s take squares of these tones since we are interested in ratios of their powers.
If isLSB = -1, that is when we want to keep \(\Sigma\) tone and reject \(\Delta\) tone, IRR will be given as:
If isLSB = +1, that is when want to keep \(\Delta\) tone and reject \(\Sigma\) tone, IRR will be given as:
That means IRR is same no matter what sideband we transmit which makes sense since IRR should only be dependent upon gain and phase error.
We want to make some measurements to evaulate \({\large \textcolor{#FEDB39}{\epsilon}}\)\( \; \& \; \textcolor{#FEDB39}{\varphi} \). These variables are tied together in IRR equation and not separable. We would need numerical techniques to solve this equation, therefore we want to simplify the equation to make IQ calibration easy and intuitive.
Assume \({\large \textcolor{#FEDB39}{\epsilon}} <<1\)\( \; \& \; \textcolor{#FEDB39}{\varphi} <<1 rad\). Let’s look at the denominator of IRR equation:
Doing similar manipulations on numerator:
We can finally write IRR equation as follows:
which shows IRR is an equation of circle in plane of \({\large \textcolor{#FEDB39}{\epsilon}}\) and \(\textcolor{#FEDB39}{\varphi}\) with radius of \(2\sqrt{IRR}\). This means there can be different combinations of (\({\large \textcolor{#FEDB39}{\epsilon}}\),\(\textcolor{#FEDB39}{\varphi}\)) that will lead to same IRR.
We can figure out \(\large \textcolor{#FEDB39}{\epsilon}\)\( \; \& \; \textcolor{#FEDB39}{\varphi} \) by applying some gain and phase errors ourselves and measuring resultant IRRs as proposed in [3].
Thus, you can calculate gain and phase errors by making three measurements. Graphically, it is the point where the three circles overlap.
(Tip: . A quick sanity check of phase error sign is to see if the IRR3 was better than IRR2. In that case, phase error that you applied partially cancelled the phase error in the system, therefore we can say the phase error in the system is of opposite polarity than what we applied. If IRR3 is worse than IRR2, then phase error in system has same polarity as of phase error you applied.)
Once you have figured out \(\large \textcolor{#FEDB39}{\epsilon}\)\( \; \& \; \textcolor{#FEDB39}{\varphi} \), you can correct the system by scaling say I channel by \(\frac{1}{1+{\large \textcolor{#FEDB39}{\epsilon}}}\) and adding phase of \(-\textcolor{#FEDB39}{\varphi} \). However, adding a phase shifter block in digital front end (before DAC in digital domain which is most likely or more plausible place to add calibration circuitry) is not very hardware friendly. We want to work with adders or multipliers. Therefore, we need to work on equivalent representation of \(\large \textcolor{#FEDB39}{\epsilon}\)\( \; \& \; \textcolor{#FEDB39}{\varphi} \) as suggested in [1,2].
Consider Q channel baseband and LO multiplication, we can write it as follows:
that is instead of saying phase error we can say it was a multiplication error as if our Q-channel LO was sin LO multiplied with \(cos(\textcolor{#FEDB39}{\varphi})\) and cos LO multiplied with \(sin(\textcolor{#FEDB39}{\varphi})\). We can make our LO error free and model phase error shown below.
so our IQ TX with gain and phase errors is equivalent to figure in bottom left that is we can model gain and phase errors by gain scaling \(\textcolor{#57ACDC}{\alpha}\) and IQ cross talk \(\textcolor{#57ACDC}{\beta}\).
We can calibrate the errors by doing opposite as shown in image below. This circuitry will be added in digital front end where data of I channel will be scaled by \(\frac{1}{\alpha}\) and \(-\frac{\beta}{\alpha}\) of Q data will be added to it. Once this data is send on I channel, it will correct the gain and phase errors of system. We can send the Q data as it is to Q channel, we don’t need to add/multiply anything to it.
We built an IQ TX in Cadence using ideal blocks like multipliers, summers and delay elements from ahdlLib library as shown in image below.
We added gain error of 0.075 to I channel BB and phase delay of 1.25 degree to Q channel LO. Our goal is now get these numbers from calibration algorithm presented above. We measure (or simulate in this case) raw IRR1, IRR2 with gain error of 0.01 applied and IRR3 with gain error of 0.01 and phase delay of 1 degree applied. Three measured numbers are shown in image below.
We made an Excel calculator (which is available to download below), plugged these numbers in, and this give us our calculated gain and phase error to be 0.071 and -1.26 degree (means delay). Hmm this is close but does not quite match the actual gain and phase errors in system which were 0.075 and -1.25 degree to be precise.
Let’s see what happens when we compute our \(\alpha\) and \(\beta\), and use them for correction of IRR. Image below show IRR before and after calibration.
IRR improves from -28dBc to -54dBc after IQ calibration. Good but not perfect. So what is missing? Remember we assumed \({\large \textcolor{#FEDB39}{\epsilon}} <<1\)\( \; \& \; \textcolor{#FEDB39}{\varphi} <<1\), this got us. Our calculator could not calculate exact gain and phase error because of this assumption. If you desire to calibrate IRR much better than -50dBc levels, then you would need to get back to original equation of IRR, and use that to calculate errors (instead of circle equation). This is also the reason we applied very small gain and phase errors (0.01 and 1 degree) so that overall gain and phase error (what we applied + what’s already in system) does not exceed our assumption of \({\large \textcolor{#FEDB39}{\epsilon}} <<1\)\( \; \& \; \textcolor{#FEDB39}{\varphi} <<1\). This is also an issue. Your system might not be able to apply such small gain and phase errors. In that case too, you need use original IRR equation. Calibration algorithm remains same. Excel can solve such equation by numerical techniques (like hit and trial).
Image below plots IRR with circle equation (dotted lines) and actual equation (solid lines). We can already see for gain error of 0.1 or more, the circle equation and actual equation don’t match. However, if gain and phase errors are small (i.e., for intrinsic IRRs better than -30dBc), circle equation is good enough.
[1] Wideband Digital Correction of I and Q Mismatch in Quadrature Radio Receivers (Hardware Friendly Implementation)
https://ieeexplore.ieee.org/document/857556
[2] I/Q Imbalance Calibration in Wideband Direct Conversion Receivers
https://ieeexplore.ieee.org/document/7790607
[3] A Low-Complexity I/Q Imbalance Calibration Method for Quadrature Modulator (Calibration Algorithm)
Summation of two vectors with phase \(\textcolor{#FEDB39}{\varphi}\) between them.
Assume a vector \(acos(\Sigma)\) and a scaled phase shifted version of it \(bcos(\Sigma+\textcolor{#FEDB39}{\varphi})\). We show in image below how can we calculate magnitude of their sum (vector Z).
RFInsights
Published: 04 June 2023
Last Edit: 04 June 2023
The post IQ Calibration appeared first on RFIC Design.
]]>We taped out a sub-6 GHz TX. Our target was -60dBc levels of LO leakage but our measurements came out to be -35dBc or so. This didn’t match our expectation from simulations and hence started months long debug as to where this LO is leaking from. We figured out it to be coming from downconversion of \(2f_{lo}\), and we share our debug story below. Get your coffee (or popcorn or just get something) and have fun learning something new below.
LO leakage was observed at TX output which was ~35dBc for NR frequency bands and ~40 dBc for frequency LMH bands even when DC offset was calibrated out. The cause of LO leakage was just 20pH inductance mismatch in TX which created 35dBc LO leakage levels. Barebones schematic of our TX is shown below. Baseband signals are received at GM cell which converts them to currents, and these currents are then passed through switching core which upconverts them to RF frequency (this is a typical Gilbert cell mixer).
LO leakage was created by inductance mismatch at source node of mixer. This node is rich with even harmonics of LO, a slight mismatch in +ive & -ive impedance at this node results in sizeable differential even harmonic currents which mix with odd harmonics of LO to land back at LO leakage in phase. LOL created by each even harmonic itself is tiny, but they add up and amount to significant LO leakage.
The mixer switch node has 2\(f_{lo}\) dips which result from tug of war between +ive and -ive transistor of mixers during LO transition. Source node follows gate. Say LO+ is high, MX+ transistor is ON, source node is following LO+. As LO+ dips, source node also goes down. However, LO- would be rising and MX- would start to turn ON and gain control of source node. Therefore, right at middle point of transition, source node stops following LO+ as MX+ has turned OFF and starts following LO- as MX- is turned ON. This brings the dip back up. This is the origin of dip. Since LO transitions happen twice a cycle, we find these dips appearing twice LO frequency.
Although the dips repeat every 2\(f_{lo}\), they contain significant energy at all of their harmonics. This makes sense mathematically because smaller they duty cycle of a pulse, the similar the energy level its harmonics will have to the limit that an ideal impulse consist of infinite harmonics all with equal amplitude.
The Fourier series of an ideal square wave consists of odd harmonics of LO. The third harmonic is 3 times lower in magnitude, 5th is 5 times lower and so on…
The 2\(f_{lo}\) dips at mixer source node consists of all harmonics of 2LO with similar energy levels at all harmonics.
where a_{DIP}, b_{DIP},.. are Fourier series coefficients.
Plots below shows V_{LO} and V_{DIP} plotted, more of a sanity check, that Fourier series is computed right, they do add up to make the signal we want.
RFInsights
Published: 13 Feb 2023
Last Edit: 13 Feb 2023
The post LO Leakage in TX appeared first on RFIC Design.
]]>Chp. 7: Quality Factor and Impedance Matching
One Must Not Tell Lies.
We have reached the finale of this saga. We have discussed how quality factor of a resonator led to signal gain and how did RF designers used that gain to boost impedance. Today we will look at how can we finally make a matching network out of this, and also a debunk a lie that has been and is continued being sold: “Bandwidth of matching network equals inverse of quality factor.”
Say you want to match 50Ω to 1000Ω at 1GHz. Let’s take two 50Ω resistors and insert a 1GHz LC resonator between them. We know that voltage across reactance is Q times larger than resistance in a series resonator. We are going to exploit this and move a resistor across a reactance to tap this voltage gain. The moment you do that, the voltage gain drops heavily because that reactance just cannot drive this small resistor (after all its not an active amplifier). What we need to do now is to boost the resistor value by 1+Q^{2} to keep tapping that voltage gain. Now you have the opportunity to choose Q. Choose it in a way that the resistor becomes 1000Ω, and that Q comes out to be 4.36 as explained in image below. So you know now that you want your LC to resonate at 1GHz with Q of 4.36. From this information, you can figure out L and C values. So, that’s that. You have a series RLC resonator which will match the impedance if you place the resistor across reactance. And once you place it, of course you raise the resistor value from 50Ω to 1000Ω to keep Q intact. Which reactance do you place it across? Capacitive or Inductive? You can choose any. If you place it across capacitor, it will be a lowpass matching network. If you place it across inductor, it will be a highpass matching network. The latter is mostly preferred choice since you can use capacitor to DC block output and inductor to provide voltage bias to chip. And this is how L-matching networks were discovered by exploiting properties of a resonator.
One of the common misconception that is found among RFIC designers (or should we dare to say a lie that is sold to them) is that bandwidth of a matching network is equal to inverse of Q. Right? You have seen this:
where FBW is fractional bandwidth \(\dfrac{\Delta \omega}{\omega_o}\) and \(\Delta \omega\) represents 3dB bandwidth around your center frequency \(\omega_o\).
(Its \(\frac{2}{Q}\) not \(\frac{1}{Q}\) because quality factor of series RLC resonator is halved – think about it, there are two 50Ω resistors – we worked out Q of 4.36 with respect to 50Ω but total series resistance is 100Ω, hence Q is halved. This is good for you because you get twice the BW)
So even though Q does not predict exact bandwidth for matching network, it does serve as a pretty good indicator of bandwidth. You can for sure infer that if Q is high, bandwidth is going to be low. So the question then is what is the bandwidth of matching network, and does it ever equal to resonator bandwidth? Unfortunately, the exact bandwidth of matching network needs to be calculated by circuit analysis. We have not found a “magic formula” for it. The good news though is that bandwidth is almost to resonator bandwidth when Q is high. This makes sense because the series-parallel transformation that we did holds across frequencies when Q is high to begin with. For example if Q is 20, then even if it varies across frequency, say from 19 to 21 across frequency, that is relatively a small change. But if you began with a small Q, say Q of 3, and now if it varies across frequencies from say 2 to 4, that is a huge change. Your series-parallel transformation with these Qs will result in very different values of boosted R (we mean R(1+Q^{2})). And since you have a fixed R attached across reactance (1000Ω in our case), your impedance transformation will be ruined, and behavior of L-match will start differing from behavior of resonator across frequency – hence different bandwidths.
Next question: how different is L-match bandwidth from resonator bandwidth. Let’s say you would settle for 5% inaccuracy in bandwidth, that is if \(\frac{1}{Q}\) gives a bandwidth which is within 5% of actual bandwidth, you would say “meh, ok, I take it, I don’t want to calculate exact bandwidth anyway, it does not matter much for me, all I care about is that I could easily design matching network with Q-factors and I have a rough idea that \(\frac{1}{Q}\) bandwidth is going to be close enough to my actual bandwidth”. In that case, we recommend to ensure Q of your L-match is greater than 5 for low pass L-match, and greater than 8 for high pass L-match, then you are guaranteed to have less than 5% bandwidth difference as shown in image below.
Image above also shows how quickly bandwidth delta grows for lower Q. For example, if Q of your L-match is less than 3, you can clearly see bandwidth delta is greater than 100% (for highpass L-match), that is your actual bandwidth is going to be much higher than what is predicted by Q of your circuit.
Alright folks – this concludes our journey from resonance to impedance matching. Hope you had fun taking this journey and it was insightful.
RFInsights
Published: 11 March 2023
Last Edit: 11 March 2023
The post Impedance Matching and Quality Factor appeared first on RFIC Design.
]]>Chp. 6: Quality Factor and Bandwidth
Q-factor is Inverse of 3dB BW. Design or Coincidence?
You have seen this
We tried looking this up on internet that how come Quality factor and Bandwidth are inversely related, and even if they were how come 3dB bandwidth comes out exactly equal of inverse of Q. Everyone throws this around as one of the “definition/formula” of quality factor not explaining how could anyone have conjured this all up. After all, the one and only true definition of quality factor is energy stored over energy loss, that is the origin of the term Quality factor, rest of the definitions are (or better should be) derived from this. This motivated us to look deep into Quality factor and bandwidth derivation and dig out some fundamental intuitions around it, and hence this article.
Now let’s change C up and down keeping L fixed, resonance frequency changes again down and up respectively, and Q changes too (this time by \(\frac{1}{f}\) fashion though because reactance of capacitor changes by \(\frac{1}{f}\) fashion)
(yellow because math is easier, \(\frac{E_S}{P_D}\) remains same over frequency as we mentioned before, the math of red curve is in appendix and leads to same conclusion what we are going to draw below).
This gives us interesting insight that your bandwidth relative to your center frequency is equal to change in Q relative to Q at center frequency. If you allow \(\Delta Q\) to be bigger, you can get wider bandwidth. Or if you decrease Q_{o}, you get wider bandwidth too. This answers our first question that how bandwidth and quality factor turned out to be inversely related, and that this relation was hidden inside the classical Q-factor formula itself.
Now to the 2^{nd} question: how come \(\Delta \omega\) turned out to be 3dB BW and not some x dB? Was it by design or a pure coincidence that our beloved half power bandwidth concept naturally landed as being equal to inverse of Q (and we mean not just proportional to inverse of Q but exactly equal to inverse of Q). To understand this, think of parallel RLC tank. When does power drop by 3dB? When current through resistor goes down to 0.707I where I was the current at resonance. For current to drop to this level, X of the tank needs to be equal to R (don’t be fooled by reactance – you might think X=R will lead to half half current division, that is not correct, because X never draws current in phase with R, so there is always a chance that R could get more from source even though X=R, if it were two Rs, then yes they draw same amount of current from source at same time (means in phase) so source current has to get divided half and half). Ok, so for 3dB power, we can write that tank susceptance needs to be equal to tank conductance:
What can you say about central tendency of this data set? If you take arithmetic mean of these points, it would come out different for each pair but you take geometric mean, it would come out equal to 1 which is correct as you can see visually in above image too. This means the central point of this data is geometric mean.
But then again, why did this happen? Answer: because of capacitor’s reactance \(\frac{1}{f}\) behavior with frequency. The reactance delta of tank is given as:
Let’s see how fast this delta changes with frequency. Take derivative of it:
This shows that reactance delta grows by \(\frac{1}{f^2}\), that is at every next frequency the new value of reactance delta is given by this much times of previous value rather than this much addition on previous value. And that is a characteristic of geometric series, hence the center frequency ends up being geometric mean, and that is also why if you look at resonator response at x times higher or x times lower frequency than resonance, you would see it develops same amplitude. But you if you were to look at resonator response at +x frequency and -x frequency from resonance frequency, you would find different amplitude.
For record, let’s just derive it in a pure mathematical too. Recall from above:
Having developed the insights behind Quality factor and Bandwidth, the situation is now ripe to proceed to matching networks – a topic for next chapter.
Derivation of Quality factor and Bandwidth relation from Capacitor’s reactance (red curve)
RFInsights
Published: 09 March 2023
Last Edit: 09 March 2023
The post Quality Factor and Bandwidth appeared first on RFIC Design.
]]>Chp. 5: Quality Factor and LC Tank Behavior in Time Domain
To develop further intuition in Q-factor and extend its application to matching and bandwidth, it is prudent to study time domain behavior of LC tank. We show how an LC tank starts up, how the voltage developed across it heads to infinity, how a finite Q-factor limits its growth, and what happens if you excite the tank with non-resonant frequencies.
Attach a sinusoidal current source of 1mA with 1GHz frequency to an LC tank which is also set to resonate at 1GHz. Let’s see how things play out.
We are going to do same experiment as above but now with an LC tank with finite quality factor. Let’s attach a resistor of 1kΩ to an LC tank set to resonate at 1GHz, and excite this tank with 1mA current source with 1GHz frequency.
If you force an LC tank at a frequency which is not natural to it (and that is everything except resonant frequency), it wouldn’t be able to develop the max voltage it could or in other words current source would never be able to deliver the power it could in resonant case. Ind and cap will always take in some current from source, leaving a little less for resistor. Therefore, voltage developed will always be smaller than a resonant case. We compare two cases. Our LC tank was set to resonate at 1GHz, we excite it with double (2GHz) and half (0.5GHz) frequency and analyze why it could not develop much voltage.
Things play out as usual. Cap and resistor start by taking all the current from source. Ind picks up the pace, and slowly starts taking current. A point comes where not enough current is available from source to keep providing for all three (ind, cap, res). Someone has to give up. Ind cannot because it does not like sudden change in current. Cap gives up and its current starts reducing. All of this looks normal transient behavior as we saw in case of resonant frequency. The difference comes from zero crossings. See now cap voltage and source currents zero crossings are not aligned which they were in resonant case. So at V1 (in left image below) cap is in a position to discharge but source still wants to go positive. Its zero crossing comes later at V2. Now instead of reverse charging the cap and ind also helping the process (as happened at V6 for resonant frequency cases described above), source tries to charge cap positively again whereas ind is still trying to reverse charge. Overall, result is that total charge or voltage build-up across cap is lesser. This goes on in every cycle, and cap is never able to develop a higher voltage. Now question is how much lesser voltage is produced compared to resonant case? Ans: the farther the zero crossing of cap voltage from source current, the lesser the voltage developed. It does not matter if source zero crossing comes earlier or later, what matters is how far away is it.
Note left and right image below are response of same LC tank. Just that left shows initial transient behavior, and right shows when things have settled.
Nothing much to say here. It emphasizes the same thing that when zero crossings are not aligned, things will not go in your favor. For example, you can observe that resistor current and source current are not in phase, so the resistor would never be able to draw all of source current and develop the max voltage it could. And they are not in phase because the way cap voltage developed and when source zero crossing came in didn’t align (V1 and V2 in left image below).
The LC tank of 1GHz resonance frequency and quality factor of ~3 is excited with different frequencies and the voltage developed across tank is plotted in image below.
Interesting thing to note here that is that if you excite at x times higher or x times lower frequency than resonance frequency, the voltage developed is same. For example, at \(1.1f_o\) or \(\dfrac{f_o}{1.1}\), the voltage developed is about 854mV. Similarly, at \(1.33f_o\) or \(\dfrac{f_o}{1.33}\) voltage developed is again same (~477mV). This tells us that a resonator behaves in a geometric fashion that is if you were to look at voltage developed at \(f_o+x\) and \(f_o-x\) it will not be same; but if you were to look at \(xf_o\) and \(\dfrac{f_o}{x}\), it will be exactly the same. How can we explain this – let’s explore that in next chapter.
RFInsights
Published: 04 March 2023
Last Edit: 04 March 2023
The post Transient response of LC Tank appeared first on RFIC Design.
]]>Chp. 4: Series to Parallel Conversion using Quality Factor
The Underrated Magic Trick
A series impedance can be transformed to equivalent parallel impedance and vice versa. This is the most underrated trick yet it is fundamental to matching network design. Math behind series to parallel conversion is simple. You want to know when a series impedance is equal to parallel impedance, so you equate them.
This means a resistor got boosted but reactance stayed same which is strange. Let’s explore the physical explanation of why is it so.
Excite a series RL circuit with voltage V_{S} as shown in image below.
Power dissipated by resistor can be given as:
Physically it means voltage across R increased by factor Q. Remember in a series RL circuit, if a resistor has V_{R} voltage, the inductor would have QV_{R} voltage. Now when you move this resistor in parallel to inductor, resistor also taps a bigger voltage QV_{R}. So if voltage goes up by Q, power goes by up Q^{2}, therefore R also has to go up by Q^{2} to keep overall power same. Or you can say if voltage goes up by Q, current has to go down by Q to keep the power same (just like a transformer where if voltage goes up by turn ratio N, current goes down by N). So ratio \(\frac{QV}{\frac{I}{Q}}\) gives you \(Q^2\frac{V}{I}\) i.e., Q^{2} times higher impedance. Ok wait, you just said that it gets boosted by 1+Q^{2}, and now you say Q^{2}. Where did 1 go? To give you intuition behind boosting (i.e., resistor tapping a bigger voltage now), we said this bigger voltage is QV_{R} but it is actually V_{S} and that is almost equal to QV_{R} for Q>>1 as revealed by Eq. (2). So, the factor 1 is there if you want to be very precise, but it wouldn’t be unfair to say Q is usually much greater than one, and to keep things simple (and memorable), we can just say impedance is boosted by Q^{2}.
Now that we argued that it makes sense for a series resistor to get boosted by factor Q^{2} when we place the resistor in parallel, you may ask why didn’t it happen to inductor because Eq. (1) tells us reactance stays almost same.
Let’s go back to series RL circuit. Inductor already had big voltage across it QV_{R}. Going from series to parallel did not get it much bigger of voltage boost. It was QV_{R} in series, and it is V_{S} now in parallel. And as stated before, QV_{R} is almost equal to V_{S} for Q>>1. Therefore inductor value only has to go up a little to keep reactive power same. If inductor also gets a boost of Q^{2}, it will draw huge reactive power, then we can’t say this parallel impedance is equal to series impedance because series inductor would have been drawing relatively small reactive power. And when Q is small, then yes boost in inductance is also visible. For Q>>1, you just don’t see much boost, so it is fair to say series and parallel reactance stays same.
Let’s run quick math to see this through. Reactive power across inductor in series RL circuit can be given as:
Note that a common misconception that exists is that this series to parallel impedance transformation is narrowband. The transformation itself is not narrow band, it is Q. Quality factor changes over frequency, and you need to update R and X values based on frequency. If you can do that, it is as wideband as you want. But you won’t be able to do that. Your typical case of use would be: you figured out what is parallel equivalent of your series circuit at one frequency, you went ahead and replaced that series circuit with parallel one. So that’s that. At that frequency, your series and parallel circuit would be behave exactly same, at frequencies nearby their response would still be similar because Q wouldn’t have changed much, but once you start looking at far off frequencies, all bets are off because Q would have changed a lot.
RFInsights
Published: 18 Feb 2023
Last Edit: 18 Feb 2023
The post Series to Parallel Conversion – Intuition appeared first on RFIC Design.
]]>Chp. 3: Passive Amplification using Quality Factor
The Story of Unsung Hero
Passives have been such an underdog. All they ever did was taking your signal away from you. A resistor dissipated it away in heat. An inductor and a capacitor exchanged it back and forth. You always resorted to a transistor to amplify your signal or an active amplifier to give you some gain. Who knew passives could amplify too, and that even without consuming any power from supply! It is about time their story is told. In this article, we are going to have a look how can a passive component like inductor or capacitor amplify the signal using its very quality factor that was actually introduced to tell folks how lossy this thing is. At the risk of spilling the beans, it is resonance that passives can employ to amplify signal, and a matching network is a living thriving example of that.
Quality of an inductor is defined by how big is its reactance (energy storage) compared to resistance (energy loss). Put mathematically, Q=X/R. This means if an inductor was excited with voltage V_{S}, not all of it will go to inductor, and a little part of it will be dropped across resistor R. Since X is Q times bigger than R (because Q=X/R), voltage divider says if V_{R} is voltage across resistor then voltage across inductor is QV_{R}, and sum V_{R}+jQV_{R} would be equal to voltage source V_{S}.
Nothing out of ordinary so far. V_{S} got divided between R and X, and there was no amplification. Just the fact that voltage across inductor was Q times bigger than resistor. Magic happens when you insert a capacitor in series, and set this capacitor value to resonate the inductor out. That means if V_{S} excites this circuit at resonance frequency, both inductor and capacitive reactance cancel out, and all of sudden your whole V_{S} is dropped across resistor. Boom. Inductor voltage still has to be Q times bigger than resistor. Quality factor remains same. We did not do anything that could affect Q. We just added a capacitor. So there you go, your inductor still has QV_{R} voltage which is equal to QV_{S} (because now V_{R}=V_{S}), and that is voltage gain of Q! And not just inductor, capacitor has same reactance (with negative sign), so capacitor has voltage gain of Q as well (with opposite polarity). And of course it all makes sense because when you do KVL, inductor and capacitor voltage being out of phase (and they are always out of phase, resonance or not) cancel out, and your V_{S} equals V_{R}. So it is as if inductor and capacitor were never there, and yet there they are.
Your L & C needs a little charge to start forever oscillations, and you instead provided it with a V_{S} source that keeps on adding energy to it in phase every cycle. As a result, voltage across L or C will blow up to infinity and beyond. You strategically placed a small resistor that keeps it from blowing up by taking whole V_{S} across it. L & C no longer gets any more energy from V_{S}, they retain their initial voltage across them which is QV_{S} and keep bouncing that around back and forth.
You say, ok cool. Passives can really amplify but now how do we use it to our benefit. Can we really tap the amplified voltage across inductor? What kind of load can I connect? What is the driving capability of this inductor?
If you connect a load across inductor, it will lower the Q, and hence your gain! Therefore, you can only connect a high impedance load if you want to have some reasonable gain. So then we can say that it has very bad driving capability or it has no power gain (you see now why they were called passives), and no kidding nobody ever used these for amplification. So much so for quality factor and gain.
What do we do now? You may rest knowing passives cannot be used as amplifiers, and you didn’t miss out anything, and you go back to your life tinkering with transistors, and take pride in being analog IC designers. Or you will not settle for this. You will find a way out to grab this opportunity to use passive amplification. And guess what. Somebody already did. Somebody realized that this was the exact problem a matching network posed “Convert a small impedance (i.e, small voltage) to high impedance (i.e., high voltage)”, “No power gain needed. Just transform my impedance”. From there on, that somebody started distinguishing itself (a little) from Analog designers, and RF designers emerged out to this brave new world of matching impedances. And that’s the story of our unsung heroes.
That is how we employ quality factor for signal gain. Now think about the circuit on right side in image above. What does it look like? A topic for next chapter – coming soon.
P.S. Nothing against analog designers. Author is an analog designer too (well most of the times).
RFInsights
Published: 14 Feb 2023 (with love)
Last Edit: 14 Feb 2023
The post Quality Factor and Gain – Passives Can Amplify Too appeared first on RFIC Design.
]]>Chp. 2: Inductor vs Resonator Quality Factor
Time (Response) is the Ultimate Truth Teller
The idea of quality factor originated from resonators and was ported to inductors later on. It was observed that a nice pure LC tank could not sustain oscillations because inductor degraded the quality of resonance. So instead of saying “bad” resonators, people started saying “bad” inductors and passed on the whole idea of quality to inductors. And so it began. Calculate inductors quality by taking ratio of imaginary to real part, and that would be the Q of inductor. It worked fine until it didn’t. Inductor started showing zero Q at their self-resonance frequency which was nor physical neither observable. You excite this inductor with impulse and you would see a damped sinusoidal response, exposing that it did have some quality, it did take some oscillations before the energy in inductor all died away. Then, why does our typical quality factor formula Q=X/R give zero Q, and why do we keep using it? Let’s dive right into it.
The definition of inductor quality factor Q=X/R implicitly assumes that inductor is free of parasitic capacitance, which is true at lower frequencies but does not hold at higher frequencies where capacitive reactance starts becoming “visible”. It substract from inductive reactance and makes overall imaginary part small. At resonance, both inductive and capacitive reactances are equal and opposite, thus net imaginary part is zero which makes our Q also zero. This is incorrect. Actual Q should be defined with imaginary part of just inductor or parasitic capacitor (one of them, not sum of them).
The problem is you don’t know how much imaginary part is coming from inductor, and how much fromcapacitor. You only get to measure the total overall imaginary, how should you find out real Q then? Go back where it all started: excite inductor with an impulse and measure the Q by using energy stored over energy lost formula of resonator.
Let’s now compare Q based on two definitions.
Think of your inductor as parallel RLC. Q can be given as:
This method is inaccurate and leads to wrong Q at frequencies closer to self-resonance.
This is the ultimate test which gives the actual Q of the inductor. Excite your inductor with an impulse, run transient simulation and count how many cycles it takes for impulse response to die out. Q is approximately equal to those number of cycles. Or if you want to be more precise, follow the experiment below.
Simulation setup below consists of inductor 2-port s-param, a capacitor to set resonance frequency, and a current impulse which comes ON for 1pS with 1A current, and then turns off (turning off current source means open circuit, so now your inductor will die its natural death, meaning you will be able to see damped oscillations). Note that quality factor is defined at resonance (that’s where it all began), therefore we added an external cap to be able to sweep resonance frequency. So say you want to find out Q at 1GHz, you will set the cap in such a way that resonance frequency becomes 1GHz.
How do you find Q factor now? Remember we said that power left after each cycle can be given as:
where P_{S} is power at start of a cycle and P_{L} is power at end of a cycle.
By one cycle, we mean one oscillation of signal, and if voltage has oscillation frequency f, power being voltage square has twice the frequency, so two oscillations of power equals one cycle. This is demonstrated in the image below. We set external cap to zero so that inductor resonates at self-resonance frequency. Take any cycle. Measure power (or voltage squared) at its peak (30.49 V^{2} in image below). Measure power after one cycle (9.16 V^{2}). Insert that in above formula and it gives 5.2 Q. You can also measure time period of one cycle and it gives out frequency of 8.2GHz, which says inductor SRF is 8.2GHz. (Does SRF match your s-param simulation, if yes, you tran simulation setup looks right)
So this is interesting. This tells us even at resonance your inductor has finite Q whereas inductor Quality factor formula would have predicted a Q of zero.
Let’s compare over the frequency range now and see how Q looks like based on two definitions.
Q from inductor and resonator definition matches at low frequency. This makes sense because at these frequencies parasitic capacitance can be ignored and your regular definition of Q=X/R gives correct Q. As we increase frequency, Q start to differ and clearly falls apart near resonance frequency. Why do we keep on using Q=X/R definition? Because it is very easy to measure, and besides inductors are supposed to be used at frequencies lower than SRF, and there Q based on two definitions match. However, we can see even at frequencies much lower than SRF (look at 2GHz which is much lower than SRF of ~8GHz), resonator method gives slightly higher Q. So if correct value of Q is important (which it is), one should always check it with resonance method.
Remember we said the problem was separating out L & C reactance. If we can figure them out, we could compute the Q this way:
So then you might wonder, how about if I figure out L and C this way:
This may work and may not work based on inductor behavior over frequency. Our assumption here is that L does not change with frequency. We figured out the inductance value at low frequency, and used that in our Q formula. This is not correct because usually inductance would decrease with frequency. Why? Inductance is defined in a loop. The return path carries the current in opposite direction, creates magnetic field in opposite direction, thus cancelling out part of forward path magnetic field, thereby reducing inductance. This phenomena becomes more and more dominant at high frequencies where return path current is concentrated just underneath the forward path. At lower frequencies, the return path current is more spread out because it faces little inductances here and there and could just take more paths in ground plane to reach its destination. Therefore, L is different at low and high frequencies. If L would have kept itself constant over frequency, you could used this method.
RFInsights
Published: 13 Feb 2023
Last Edit: 13 Feb 2023
The post Quality Factor Formula – Inductor vs Resonator appeared first on RFIC Design.
]]>Chp. 1: Origin of Q-Factor
The Deadly Beginnings
Let’s start from a capacitor C. Charge it to 1V. Now connect it to a resistor R. What will happen? Capacitor will lose charge exponentially. You would say, ok, my time constant \(\tau\) is RC, so in about 5\(\tau\) seconds, my capacitor would have lost it all because that’s how an exponential function goes.
Ever wonder though why did it have to be an exponential function? Why couldn’t it be linear or some other function for that matter? Asking such questions is important to build upon fundamentals. The way current is drawn from the capacitor depends on the load connected to it. A resistor is such a load which demands from the capacitor to send the charge in a way that rate of change of charge is equal to charge itself at any point in time. Let’s do some math to see this.
What is something whose derivative is equal to its current value? Think about it. It’s an exponential function.
Therefore, the charge (or the derivative of charge which is current) decays exponentially. A resistor will always draw current from the capacitor exponentially. Story changes for an inductor.
Let’s start again from a capacitor C. Charge it to 1V. Now connect it to an inductor L. What will happen? Capacitor will lose charge in a sinusoid fashion.
When you connect this charged capacitor to an inductor, the capacitor will start losing its charge, so the voltage would start decreasing Current would start flowing and inductor will begin to expand its magnetic field. When the capacitor has lost it all (at T/4), and there is no charge to flow, current would have collapsed to zero except that inductor resists the sudden change in current (because of back EMF). So, the inductor keeps the current flowing in same direction and capacitor starts getting charge from inductor, and charges with opposite polarity now. A time (T/2) comes when inductor has lost it all (magnetic field has collapsed) and all the charge is transferred to capacitor. Capacitor will discharge through inductor again, then inductor discharges through capacitor again, and this goes on. The cycle repeats. We call this behavior resonance, and the LC tank as resonator.
The questions arise:
Therefore, the charge on capacitor (or voltage as V=Q/C) is exchanged with inductor in a cosine fashion, and the time period of this exchange is T/4 (meaning 4 charge exchanges happened in one cycle)
How fast is the charge exchange in LC compared to RC? Assume R=C=L=1, the charge on capacitor would decay in 5 sec for RC and \(\frac{\pi}{2}\) sec for LC which is about \(\pi\) times faster than RC!
Let’s go back again. Charge the capacitor C to 1V. Connect it to a resistor R and inductor L. What will happen? Capacitor will exchange charge with inductor again in a sinusoid fashion except that resistor will demand the charge exponentially. Energy exchange may go on for a couple cycles until the resistor has dissipated all the charge away . We would call this a bad quality resonator which couldn’t sustain resonance. I think you are getting an idea where we are heading. Let’s keep developing our thought:
If we were to compare two resonators say L_{1}C and L_{2}C where L_{1}>L_{2}, say both have a resistor R in parallel to them. Do both these resonators have same quality (after all R is same)? No. Turns out that L_{2}C is a better resonator than L_{1}C (L_{2}C sustained more oscillations). So, then that’s how folks started quantifying resonators. Look at how many oscillations, and that is the quality factor of a resonator (well sort of, not very precise, but visually if you were to look at a resonator response, you would just count the number of cycles it sustained oscillation, and that would be your approximate Q factor of circuit, and this is happens to be an interview question)
Ok, visually we can determine Q-factor by looking at number of cycles. But how should we quantify it mathematically? Is there a way by looking at RLC values, we could tell the quality of a resonator? That is what folks also felt and ended up discovering Q=R/X relation. Here’s how it would have happened:
So, for resonator to be a good quality or let’s say have at least one cycle of oscillation, we would say, hey 5RC time of charge decay in a pure RC should be greater than T_{0} time of oscillation in a pure LC. This way we would make sure that at least one cycle of back and forth charge transfer between capacitor and inductor happened before resistor could lose it all away. Let’s write that down mathematically:
This tells us that if \(\omega_0\)RC is equal to one, we could hope to see at least one oscillation (because we would have ensured 5RC decay is longer than one oscillation time period). If it is two, we would see two oscillations. That’s it. We have arrived at our metric of Quality for resonators. The term \(\omega_0\)RC is what we can call as quality factor. You don’t need to count cycles now. Just evaluate \(\omega_0\)RC for resonator and that will be the number of cycles your resonator is going to survive. A little manipulation reveals, that \(\omega_0\)RC is actually a ratio of R and X.
So, quality of a resonator depends on all, R & C & L. It’s not just R, or RC time constant or LC resonance frequency. Everything put together in above expression is your measure of Quality. Now you can also appreciate why L_{2} in above example gave higher Q than L_{1}. This concludes our discussion on how the term Quality factor originated, how was it used to compare resonators by looking at number of cycles, and how did those cycles ended up being equal to R/X.
(Caution: Lots of math coming, good if it has been long and you want to refresh couple things, best if you really want to see things through, bad if you are like young me who didn’t appreciate math)
Let’s try to derive response of a parallel RLC tank. We can write currents as:
This is a second order linear homogenous differential equation with constant coefficients.
Linear homogenous differential equations with constant coefficients can be reduced to characteristic equations and solve algebraically as follows:
where K_{1} and K_{2} can be found through initial conditions. At t=0, we had capacitor charged to 1V (let’s say V_{o} to make it generic). Let’s put that in.
At t=0, the inductor had zero current flowing through. Let’s put that in.
Put this in (1), we get our K_{1} and K_{2}
Let’s plug these in our general solution, and simplify to see a more plausible form of V(t):
Plug these in equation above:
and finally, we have done it, we have our rigorous math exercise telling us exactly the same thing: your RLC is a resonator, oscillating at frequency \(\omega_{d}\) (which is lesser than \(\omega_o\)), with a starting phase of \(\phi\), and amplitude is scaled by a decaying exponential.
Also interesting to note that, in pure RC, voltage dies out in 5RC seconds, but in RLC, voltage dies out in 10RC.
This is the precise relation between Q and N. Q is equal to 1.6 number of cycles. So for example, if Q is 5, you should see about 8 cycles of oscillation before it is all vanished.
We inserted V(t) equation in Desmos, go ahead and play with Q factor below, count the number of cycles.
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]]>As with any circuit, a TX comes with two basic impairments: distortion and noise. Some of these fall very close to the signal band, get transmitted out of antenna, and cause emissions in adjacent channels measured as ACLR. And some of these fall a little far away from signal band, get attenuated through duplexer, and make it to your own RX causing degradation in sensitivity of your own RX. Such emissions from your own TX to your own RX at the RX frequency are referred to as receive band noise (we emphasized the RX frequency, because if it is not at the RX frequency then we refer to them as out of band blockers in RX lingo, and make it more of an RX team issue to deal with).
Note that while receive band noise is primarily a concern for your own RX, it also gets transmitted out of antenna (just like any regular emission), and that is also an issue but chances are you have already taken care of it while meeting ACLR specs over adjacent bands, now is the time to take care of your own RX which will be the biggest victim to this received noise as other folks will get a much smaller copy of this noise because of path loss from your antenna to someone else’s antenna. Also note that receive band noise is only an issue in FDD scenarios, in TDD RX is OFF when TX in transmitting, so we don’t care about noise reaching RX.
Let’s take a real life example. Say we are operating in FDD band N25. We have our 20MHz TX signal parked at left edge of TX frequency band, and we have RX operating at the right edge of RX frequency band. This is the worst case scenario as RX is only 15MHz away from TX. Say our TX chip is giving out -10dBm output power and -160dBm/Hz noise at 15MHz offset (this number is great, you did an awesome job as tx designer). Let’s see what happens when this noise makes it to RX. We have traced noise numbers along TX chain in the image below.
You can see how DA and PA amplified the noise to -85dBm/Hz level, it is so huge that we had to use a 80dB rejection duplexer, and even after that we are left with -165dBm/Hz of noise power at RX input which degrades our RX sensitivity by 7.8dB. This is a motivation for you to reduce your driver and power amplifier noise in addition to TX RFIC noise.
We are attaching the spreadsheet for above calculations. Play with different parameters of system to understand how you can budget noise between various blocks of TX. Also you can see in the image below how RX was passing 3GPP sensitivity requirement but now your TX noise made it fail.
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]]>EVM is one of the key TX design spec. EVM is a measure of signal quality. It is a measure of in-band distortion and noise while ACLR was a measure of out-of-band distortion and noise. Funny enough that since it is in-band, you do not care as much about it as ACLR. If distortion is leaking in neighboring band, you have to fix it right away. If distortion is falling in-band, you are like:
“ahh okay, will see how much do I need to fix it, maybe I can still play some trade-offs in my system to do something about (and by the way I didn’t impose very demanding distortion specs on myself, things fall in-band, I take care, these ACLR folks are outrageous, they just don’t want you to emit anything outside), enough blabber, I will fix it, don’t worry, let me see what’s wrong with ACLR first”
Okay, but how would you fix EVM? We need need to decompose EVM into different metrics to understand what factors contribute to it, and thereby optimize/debug it with proper insights.
TX EVM is composed of three main components: distortion, noise and leakages as shown below.
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]]>A TX is required to comply with Spectral Mask which basically says you cannot transmit x amount of power outside of your given frequency band. As with everything in life, TX is not ideal and ends up spilling some power in adjacent bands which is measured as ACLR. This power consists of distortion and noise. Distortion power is straightforward to estimate. You run a two-tone test and see what are IM3 and different intermod levels. How do we estimate how much noise is limiting our ACLR? We integrate the noise across bandwidth. Let’s take a look at how TX noise and PLL phase noise integration is done.
Consider your LO signal has phase noise. It can be modelled as:
Now, consider a baseband signal to be an OFDM symbol. We know it is composed of multiple cosines (subcarriers), it can be written as:
Add noise to baseband signal:
which says noise is sum of cosines where \(\phi_k\) is the phase angle of the k_{th} component, and the number of components are N = N_{2}-N_{1}+1. Details don’t matter, you can look it up here [1]. Just think n(t) as some noise.
Notice how LO phase noise has transferred to upconverted baseband signals. This means that every upconverted baseband tone will have LO phase noise profile across it. Also see, all of baseband noise n(t) is also upconverted around LO. This means baseband noise is additive in nature, thus only upconverts to band center (LO) where as LO phase noise is multiplicative and upconverts to all the signal tones.
Now that we know baseband noise is additive, we can insert baseband noise profile (flicker+thermal) at center of band (or more precisely at LO frequency) and integrate the noise which lands in ACLR region. That will be the TX noise contribution to ACLR. This is shown in image below.
Since LO noise is multiplicative, we need to insert it across each subcarrier. Simulate and export LO phase noise data. Scale it down by number of subcarriers. Add this scaled down profile to each subcarrier, integrate the noise falling in ACLR region from each subcarrier and then sum it all up (you can try 15log() summation as this noise will be partially correlated since all subcarrier have same noise profile). This will be PLL noise contribution to TX ACLR.
Total noise in ACLR band will be the sum of TX noise and PLL noise powers.
[1] “Noise Power Fluctutations and Masking of Signals”. W.M. Hartmann et al. Physics Department. Michigan State University. https://web.pa.msu.edu/acoustics/pumplin1.pdf
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]]>This is part 3 in series of two tone intermodulation distortion. When we usually talk about two tone intermods, we mean it for two RF tones for which 2nd harmonics or even order terms fall far away, and we say we only care about IM3 and IM5 because they are close to our signal. That is clearly not the case for two BB tones. Here everything falls either in-band or very close to the signal band leaking into adjacent channels. That is why baseband emissions are one of the top contributors in ACLR. Let’s have a visual look at baseband tones intermodulation.
Image below says it all. You can see how 2nd order terms (BBHD2 & IMD2s), 3rd order products (BBHD3 & IMD3s), 4th order products (BBHD4 & IMD4s) and 5th order products (BBHD5 & IMD5s), they all fall in ACLR zone. On the other hand, IM3 and IM5s (the ones you hear most about), envelope, and some IMD4s fall in-band degrading signal quality, and thus EVM.
For this case, you see distortions are more spread out. You get mix-and-match of odd and even order non-linearities in-band and out-of-band.
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]]>This is part 2 in series of two tone intermodulation distortion analysis. Whether you are optimizing linearity or debugging it, you want to understand what are different distortion products, how do they get generated and what are they made of. For example, IM3 is made of odd order non-linearities: 3^{rd} order has the highest contribution but 5^{th}, 7^{th} etc. also add to it. Another example, you might have seen IM2=2*HD2 in textbooks but when you go measure that is not the case. Why? Textbooks conveniently ignore higher order terms and just derive IM3 from 3^{rd} order or IM2 with 2^{nd} order assuming a weakly non-linear system. That is little wishful. We are extending the analysis to 5^{th} order which is an optimum strike between over-analysis and under-analysis.
Assume a non-linear memory-less system whose output has up to fifth order of non-linearity. We can relate output and input as:
Lets excite this system with two tones:
Output can be written as:
Square terms:
Cubic terms:
Quadratic terms:
Color coding: DC is white, Signal is green, Square terms are yellow, Cubic orange, quadratic sky blue, and pentic red.
The All Mighty IMD Table:
Let’s put things in perspective. We took a CMOS transistor, excited it with some input voltage and looked at the output current to see relative distortion levels (yes we are looking at gm non-linearity). It gave us following:
It says, in a typical circuit, you would get -25dBc HD2, -40dBc HD3, -55dBc HD4 and -60dBc HD5 (without optimization of course, just raw typical numbers). We derive our polynomial coefficients from these, and now we have an idea of typical values of a_{1},a_{2},a_{3},a_{4} and a_{5} in a non-linear system. Also note the signs, typically our circuits are compressive which means when you input big sin wave, output looks more like a square wave, and you know for a square wave (composed of cosines) you have 3^{rd} harm out of phase with fundamental, and 5^{th} harm is in phase (that is what our table also says in the “sign” column). Signs for even terms are very subjective, they can be anything really.
Let’s take these co-efficients and insert in our “The All Mighty IMD Table” to have a visual picture of relative levels of IMDs.
We filtered out tones below -70dBc in above image (just to unclutter). What you should worry about is that HD2s and beat terms are even bigger than IM3 in a typical system, and similarly IMD4 products are bigger than IM5s. That means even order non-linearities are greater than odd order, but it so happened that odd order fell close to your signal and became more critical because you always said you could filter out far-flung even order terms. Well, that may not always be the case. Consider a very wideband system:
When you start spacing out signal tones, non-linearities start spreading out, thus coming closer to your desired signal. Above image shows that IMD4 landed between IM3 and IM5. So now you need to optimize for IMD4 (or at least keep this guy in mind) in addition to IM3 and IM5. We must remark that this scenario happens for very wideband systems (e.g., say 2.7GHz center RF frequency, and signal bandwidth from 2.4GHz to 3GHz (that’s fractional BW of 22%!), in this case IMD4 lands on IM5).
Another insight you can get from this numerical example:
Why did this happen? Because textbook ignored higher order terms. We didn’t (well we ignored very high order terms, gotta stop at some point right?). Download our spreadsheet below for this numerical example.
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]]>We decided to write this articles because there are only so many different models of a transformer that exist. Analog IC designers, RFIC designers and mm-wave IC designers – they all understand transformers a little differently. Enough is enough. We are putting together a list of different models (with derivations of course) for your quick reference, and we also show you THE one favored by the most folks.
Consider a transformer as shown in image below.
Applied source V_{1} consists of two voltage drops: First, the voltage drop produced by the current I_{1} which is generated from the V_{1} itself. And second, the voltage drop produced by induced current I_{2} which is actually generated by V_{2}. Therefore, we can write V_{1} and V_{2 }as:
or
Recall that this looks much like a 2-port Z-parameter matrix given as:
Therefore, we can say:
The equivalent circuit for Z-parameters of a reciprocal 2-port network can be given as:
This is the base model of a transformer. It says, if I_{2} were zero (i.e., secondary is open-circuited), then applying V_{1} and measuring I_{1} will only reveal L_{1} (which makes sense as primary inductance is L_{1}). However, the moment you apply some V_{2}, mutual inductance M will lead to slightly different I_{1}, thus V_{1}/I_{1} will no longer give you L_{1} impedance. It will be different. What shall it be? Let’s improve this base model to answer such questions. Before that, let’s get done with some FAQs.
Q: What is difference between M and k?
A: M is real deal. M is real physical thing. M is mutual inductance which is a way of saying how much “extra” voltage is produced in one coil due to magnetic field “coupling” created by I_{2} in second coil. k is just a way of saying coupling is not perfect.
Q: Define M
A: \(M=\sqrt{L_1L_2}\)
Q: Define k
A: k is saying hey this M is going to be less than its value because coupling ain’t good so you’d better write M as \(M=k\sqrt{L_1L_2}\) where \(0 \le k \le1 \)
Q: Base transformer model shown above didn’t talk about turn ratio. How to think of turn ratio?
A: Consider an ideal transformer with turn ratio (N_{2}/N_{1}) as n
Practical transformer: Hey coupling ain’t perfect, so terminal relations of Eq. (2) won’t hold. Add k.
People would like to separate out turn ratio and keep it as a clear visible metric to quickly transform impedance. So you won’t see the base model being used anywhere at least in IC design.
What do people want? A model like this:
Think about the terminal relations of the black box ? now. They are:
We want to know what kind of transformer can we put here which in series with ideal transformer of 1:n would produce same results as original transformer. Start with writing the z-matrix:
Comparing it with Eq. 1 gives us:
This says our black box is actually a transformer like this:
Engineers just wouldn’t like to see M. They work with k. So let’s get rid of M, ready when you are.
It’s not hard to prove that k^{2}L_{1} on primary side becomes L_{2} when moved to secondary. Just multiply k^{2}L_{1} by n^{2} (because remember an ideal transformer transforms impedance by n^{2})
There is yet another genre of folks who just don’t like to see k in their turn ratio n. It is more intuitive for them to think: “hmm that’s how I need to size my L_{1} and L_{2} to get this turn ratio n”, whatever k does, it does. We will model it separately. Oh well. Okay. So let’s try to take k out of n and see how our model looks like.
We know from Eq. (3) that
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]]>Power Amplifiers (PA) are in the transmitting chain of a wireless system. They are the final amplification stage before the signal is transmitted, and therefore must produce enough output power to overcome channel losses between the transmitter and the receiver. In this tutorial, we are going to have a detailed look at mm-wave PA design.
The first step in designing a PA is topology selection. Let’s look at the standard amplifying blocks shown in image below. We have common emitter (CE). It has high input impedance and high output impedance which is great. Reverse isolation is poor because there is miller capacitance between collector and base. And also the output power is limited by the collector emitter breakdown voltage, BV_{CEO}.
The next candidate then is common base amplifier (CB). Common base voltage swing would appear across collector and base. CB can produce higher output power as it we can put higher voltage swings voltage across it compared to CE (BV_{CBO} > BV_{CEO}). But, the input impedance is very low, making it very difficult to drive.
Next we have cascode, which has properties of both common base and common emitter. Upper transistor works as common base, generating higher output power. Lower transistor is common emitter, providing higher input impedance. Also there is no direct feedback capacitor from output to input, thus reverse isolation is also very good. It makes sense to go for cascode, so go the most of mm-wave PA designs.
PAs are designed using loadpull simulations because:
Here’s how to launch Loadpull workbench in Keysight ADS software, as shown in image below.
We have chosen cascode as our core amplifier and connected it to the load pull instrument as shown in image below. Our goal was 10dbm. Let’s do 13dBm in order to accommodate losses (3dB higher? let it be, this is 94GHz you are talking about).
We are going to run multiple load pull simulations to optimize device size, bias, and supply voltage:
Run loadpull simulation. Start with approximate bias settings, input power, device size etc. and tune them as you optimize loadpull impedance. We start with 0.8V VBE of input transistor, 1.8V at cascode base and 4V VCC. Please read plots below from left to right. These are loadpull iterations we did. We highlight in yellow color what we changed in each simulation.
Insert the loadpull impedance (center point of converged contours shown in bottom right image above) in sourcepull setup and run sim.
Run loadpull. Use loadpull impedance and Run sourcepull. Use sourcepull impedance and run loadpull. Repeat this a couple times until you have converged to a loadpull and a sourcepull impedance.
We got following:
Comment: We don’t need to overdrive the PA, so Pavs has been decreased. Alright, we are done with loadpull of mm-wave pa.
We biased in class AB which would typically have efficiencies around 50-60%. This is true for low frequencies where parasitics can be ignored and design follows the simple math. But at 94GHz even the fF of capacitors matter! And they make voltage and current waveforms overlapping, so there is power dissipation across the device which degrades the efficiency.
Terminate the PA with load and source impedances found above and do harmonic balance analysis with power sweep. Setup is shown in image below.
Results are very close to loadpull simulations but not exactly the same. Why? Because harmonic impedances are not open-circuited in this case. We observe our peak PAE
Before we proceed, let’s just see for the sake of our understanding, the difference between small and large signal impedance. Run an s-param simulation and compare how does it look against source and loadpull impedances. We found that sourcepull impedance was very close to S11 but loadpull was very different than S22. It makes sense because the output experiences large voltage swings, and hence its large signal impedance is different than small signal s-param impedance.
You clearly see in image below that if you were to proceed with small signal matching of your PA, your Pout and PAE would have been crap.
Four possibilities using L-match. Choose the one which suits your needs.
We have chosen the first one with shunt inductor and series capacitor. We will bias out collector through shunt inductor and use this capacitor as DC block for output. Hence, this network serves as a matching network as well as bias T for mm-wave pa.
We are on track. Pout and PAE after matching match loadpull simulations.
We added Q to inductors. Two things happened. First because of the loss at output inductor, our Psat has decreased by 0.5dBm and our PAE has decreased by 12%. Second, the gain saw a big reduction because it takes into account both input and output losses. Now, our peak PAE is not at -5dBm but -2dBm.
Replace ideal voltage sources with realistic models:
Adding wirebond inductances and bypass caps didn’t impact Pout or PAE. Phew. Let’s move on.
Use s-param simulations and StabFact in ADS. Note that there is ever going debate on what is the correct test for stability as some folks do not like small-signal stability tests on devices which operate in large signal. You should do your due diligence to run different tests for stability after you are done with design (like run a transient sim, no one would argue on that). However, to progress through design optimization stages, we think k-factor or mu are good enough. So, let’s run k-factor (StabFact in ADS) and see what happens.
Add a series resistor at base to stabilize source and make sure bypass cap is sufficient for low frequencies.
Although PA is stable now, add a de-qued capacitor at VCC node just as a precaution (because we know this node has tendency to get unstable)
Upper base node is highly prone to oscillation in mm-wave power amplifiers. Even a little parasitic inductor (~5pH) can make PA oscillate. Add a parasitic inductor, and see what happens:
The only way forward here is to reduce parasitic inductance as much as possible or introduce loss. We show that adding \(5\,\Omega\) resistance solves the issue (StabFact > 1)
We are going to use a process which has 5 thin metal layers (M1-M5) for general purpose routings, 2 thick top layers (TM1-TM2) used for RF routing, MIM capacitors and Rsil Rppd resistors. This is how a transistor looks in our PDK:
Make a floor plan of where do you want things to be. We start with upperbase connection before anything else since we know this node needs the lowest inductance possible for stability of mm-wave cascode.
You can use whatever EM software you have available. We had Sonnet. In the image below, we show routing from the base node of cascode to the top metal layer. In Sonnet, your structure is enclosed in a closed metal box which serves as a ground reference. “BoxWall” is a port which connects between this metal box and your feedline and then you de-embed your feedline (it’s similar to Waveport in HFSS software). Read more on Sonnet in [1] & [2] if you are interested.
Worth mentioning that a common misconception about de-embedding: it completely de-embeds feed line. Not correct. Fringing fields are not de-embedded as shown in image below [2].
Export s-param model from EM sim. Attach it to your schematic, and run HB and s-param sim. We see that k-factor is greater than 1 showing that it is unconditionally stable. We did a good job in minimizing the inductance of this connection.
Connection from transistor collector on M1 to layer to topmost layer (TM2).
Insert exported s-param in schematic and run sim. Results look great. Very little drop in Pout and PAE.
Add matching network capacitor in EM sim
Insert exported s-param model in schematic and simulate.
We are doing this step by step to keep track of where do we lose performance. Losing 1% PAE or 0.2 dB of power is not a big deal, it maybe because matching is not EM optimized yet. Keep on adding more stuff and optimize it later altogether (optimize in small groups if things get out of control).
We added output matching inductor. Let’s run the sim.
Results look great. At this point, simulate all the EMs together (base connection, output cap and ind). Optimize and re-simulate. Few iterations and you should be close (however, we should mention this process of optimization is very tiring and you don’t actually do “few”, you do a lot EM sim, optimize, EM sim, optimize…it’s frustrating. Don’t worry, AI is coming to help, and beside in Industry you don’t need to do this, they have hired folks to do these optimization for you)
Here is how our optimized layout for upperbase connection and output matching looked like. We did not do input matching. Give us a break. We think you got a pretty good idea what’s the process like. This completes our design of mm-wave PA.
These are the final results. Just for fun, we compare with ideal components vs layout. We see 1dB loss in Pout, 14% drop in PAE and about 3dB drop in gain. Also interesting to note that s-param look quite the same. At this point, you have one design ready and you know what to expect from a 94GHz PA. Now is the time for you to get creative and start thinking of matching networks other than L-section to reduce the loss. There is an optimum for matching network order that give you the lowest insertion loss. Yes, lower number of elements are not always lowest in loss. Intuitively adding sections can decrease the insertion loss since it also lowers the network Q factor. Adding too many sections, though, can counterbalance this benefit. Check last two slides of Niknejad.
We taped out a PA designed at 28GHz using above steps. Image below shows chip photo.
This is how it looked like in measurement:
We hope you enjoyed our mm-wave PA design tutorial. Please leave us a feedback if you find typos or mistakes.
[1] http://muehlhaus.com/wp-content/uploads/2011/07/Sonnet-Ports-RFIC.pdf
[2] http://www.sonnetsoftware.com/support/downloads/manuals/st_users.pdf
[3] http://literature.cdn.keysight.com/litweb/pdf/5989-9594EN.pdf
[4] http://rfic.eecs.berkeley.edu/~niknejad/ee242/lectures.html
[5] https://www.microwaves101.com/encyclopedias/load-pull-for-power-devices
Equations for Harmonic Balance Plots:
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